Datasheet

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SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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6
FUNCTIONAL BLOCK DIAGRAM
Logic and Control
12 Bit
Pipeline
ADC
S/H
S/H
S/H
S/H
Single
Ended
and/or
Differential
MUX
+
–
V
REFM
1.5 V
3.5 V
1.225 V
REF
12
Buffers
2.5 V
Control
Register
AV
DD
DV
DD
AGND DGND
REFOUT
BV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1
BGND
REFP
REFM
AINP
AINM
BINP
BINM
CONV_CLK
CS0
CS1
RD
WR (R/W)
REFIN
V
REFP
SYNC