Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TQFP 48

SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005

    

     







FEATURES

D 14-Bit Resolution

D 1, 3, and 8 MSPS Speed Grades Available

D Differential Nonlinearity (DNL) ±0.6 LSB Typ

D Integral Nonlinearity (INL) ±1.5 LSB Typ

D Internal Reference

D Differential Inputs

D Programmable Gain Amplifier

D µP-Compatible Parallel Interface

D Timing Compatible With TMS320C6000 DSP

D 3.3-V Single Supply

D Power-Down Mode

D Monolithic CMOS Design

APPLICATIONS

D xDSL Front Ends

D Communication

D Industrial Control

D Instrumentation

D Automotive

DESCRIPTION

The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8

MSPS, single supply analog-to-digital converters (ADCs)

with an internal reference, differential inputs,

programmable input gain, and an on-chip

sample-and-hold amplifier.

Implemented with a CMOS process, the device has

outstanding price/performance and power/speed ratios.

The THS1401, THS1403, and THS1408 are designed for

use with 3.3-V systems, and with a high-speed µP-

compatible parallel interface, making them the first choice

for solutions based on high-performance DSPs such as

the TI TMS320C6000 series.

The THS1401, THS1403, and THS1408 are available in a

TQFP-48 package in standard commercial and industrial

temperature ranges. The THS1401, THS1403, and

THS1408 are also available in a PQFP-48 package in

automotive temperature range, and the THS1408 is

available in a PQFP-48 package in military temperature

range.

PGA

0..7 dB

REF

14-Bit

ADC

Buffer

14 15

CONTROL

LOGIC

REF+

REF−

IN+

IN−

D[13:0] + OV bit

A[1:0]

CLK

1.5 V

VBG

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (28 pages)

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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 FEATURES D 14-Bit Resolution D 1, 3, and 8 MSPS Speed Grades Available D Differential Nonlinearity (DNL) ±0.6 LSB Typ D Integral Nonlinearity (INL) ±1.5 LSB Typ D Internal Reference D Differential Inputs D Programmable Gain Amplifier D µP-Compatible Parallel Interface D Timing Compatible With TMS320C6000 DSP D 3.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted.(1) Supply voltage, (AVDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Supply voltage, (DVDD to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 THERMAL CHARACTERISTICS(1) TYP Thermal resistance, junction-to-ambient, ΘJA Thermal resistance, junction-to-case, ΘJC PFB package 85.9 PHP package 28.8 PFB package 19.6 PHP package 0.79 UNIT °C/W °C/W (1) Thermal resistance is modeled data, is not production tested, and is given for informational purposes only. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Supply voltage, AVDD, DVDD 3 3.3 3.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 81 90 mA 5 10 mA 270 360 mW Power Supply IDDA IDDD Analog supply current Digital supply current AVDD = 3.6 V DVDD = 3.6 V Power AVDD = DVDD = 3.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (Cont.) Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 1.425 1.5 1.575 UNIT Reference Voltage Bandgap voltage, internal mode V Input impedance 40 kΩ Positive reference voltage, REF+ 2.5 V Negative reference voltage, REF− 0.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION sample timing The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results appear on the digital output 9.5 clock cycles after the input signal was sampled. S11 S9 S12 S10 Analog Input tw(CLK) tw(CLK) CLK td Data Out C1 C2 C3 Figure 1.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION read timing (15-pF load) PARAMETER tsu(OE−ACS) ten Address and chip select setup time tdis th(A) Output disable MIN TYP MAX 4 ns Output enable 15 10 Address hold time th(CS) Chip select hold time NOTE: All timing parameters refer to a 50% level. ns ns 0 ns th(CS) OE ten tdis DATA D[13:0] OV th(A) A[1:0] X ADDRESS Figure 2.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION write timing (15-pF load) PARAMETER tsu(WE−CS) tsu(DA) Chip select setup time th(DA) th(CS) MIN TYP MAX UNIT 4 ns Data and address setup time 29 ns Data and address hold time 0 ns Chip select hold time 0 ns 15 ns twH(WE) Write pulse duration high NOTE: All timing parameters refer to a 50% level.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS POWER vs FREQUENCY SUPPLY CURRENT vs TIME 284 90 282 80 70 I CC − Supply Current − mA Power − mW 280 278 276 274 272 270 60 50 40 30 20 10 0 268 0.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 0 fs = 3 MSPS, fI = 1 MHz, −1 dB Output − dB −20 −40 −60 −80 −100 −120 −140 0.1 0.4 0.7 1.3 1 f − Frequency − MHz Figure 7 FAST FOURIER TRANSFORM 0 fs = 8 MSPS, fI = 1 MHz, −1 dB Output − dB −20 −40 −60 −80 −100 −120 −140 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY 2 fs = 3 MSPS 1.5 1 0.5 0 −0.5 −1 −1.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY 1 0.8 fs = 3 MSPS 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 13 DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY 1 0.8 0.6 fs = 8 MSPS 0.4 0.2 0 −0.2 −0.4 −0.6 −0.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION registers The device contains several registers. The A register is selected by the values of bits A1 and A0: A1 A0 Register 0 0 Conversion result 0 1 PGA 1 0 Offset 1 1 Control Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default values (were applicable) show the state after a power-on reset. Table 1.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 PRINCIPLES OF OPERATION Table 4. Control Register, Address 3, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES Table 5.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass filters to attenuate out of band noise. The input range on both inputs is 0 V to AVDD. The full-scale value is determined by the voltage reference. The positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals −∆REF.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 10 kΩ + 10 kΩ 10 kΩ 10 kΩ IN+ 100 pF REF+ THS1401/3/8 22 Ω − IN− 100 pF + 10 kΩ REF− 10 kΩ Figure 21. Single-Ended With Level Shift The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: ∆IN+ [V] OUTPUT −∆REF − full scale 0 0 ∆REF + full scale Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION internal/external reference operation The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external precision reference in case very high dc accuracy is needed. The REF+ and REF+ outputs are given by: ǒ Ǔ REF )+ VBG 1 ) 2 and REF– 3 If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF− = 0.5 V and ∆REF = 2 V.
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www.ti.com SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005 Revision History DATE 9/05 REV D PAGE SECTION 1 — Updated page 1 format and layout. 1 — Moved funtional block diagram from page 2. 2 — Moved Terminal Function table from page 3. 2 — Moved Absolute Maximum table from page 4. 3 — Moved package pinout from page 1. 3 — Moved Ordering Options table from page 2. 15 16 DESCRIPTION Principles of Operation Table 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.