Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Current feedback SOIC 8

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

OUT

TOTAL HARMONIC DISTORTION

FREQUENCY

TYPICAL ARBITARY WAVEFORM

GENERATOR OUTPUT DRIVE CIRCUIT

−90

−80

−70

−60

−50

−40

−20

1 M 10 M 100 M

f − Frequency − Hz

Total Harmonic Distortion − dBc

G = 5,

= 715 Ω,

= 100 Ω,

= ±15 V

100 k

−30

= 20 V

= 10 V

= 5 V

= 2 V

−

THS3092

−

THS4271

IOUT1

IOUT2

DAC5686

THS3092

THS3096

SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006

HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK

OPERATIONAL AMPLIFIERS

• Low Distortion

The THS3092 and THS3096 are dual high-voltage,

low-distortion, high speed, current-feedback

– 66 dBc HD2 at 10 MHz, R

= 100 Ω

amplifiers designed to operate over a wide supply

– 76 dBc HD3 at 10 MHz, R

= 100 Ω

range of ±5 V to ±15 V for applications requiring

• Low Noise

large, linear output signals such as Pin, Power FET,

– 13 pA/ √ Hz Noninverting Current Noise and VDSL line drivers.

– 13 pA/ √ Hz Inverting Current Noise

The THS3096 features a power-down pin ( PD) that

puts the amplifier in low power standby mode, and

– 2 nV/ √ Hz Voltage Noise

lowers the quiescent current from 9.5 mA to 500 µA.

• High Slew Rate: 5700 V/ µs (G = 5, V

= 20 V

)

The wide supply range combined with total harmonic

• Wide Bandwidth: 160 MHz (G = 5, R

= 100 Ω)

distortion as low as -66 dBc at 10 MHz, in addition, to

• High Output Current Drive: ±250 mA

the high slew rate of 5700 V/µs makes the

• Wide Supply Range: ±5 V to ±15 V

THS3092/6 ideally suited for high-voltage arbitrary

waveform driver applications. Moreover, having the

• Power-Down Feature: (THS3096 Only)

ability to handle large voltage swings driving into

high-resistance and high-capacitance loads while

maintaining good settling time performance makes

• High-Voltage Arbitrary Waveform

the THS3092/6 ideal for Pin driver and PowerFET

• Power FET Driver

driver applications.

• Pin Driver

The THS3092 is offered in an 8-pin SOIC (D), and

• VDSL Line Driver

the 8-pin SOIC (DDA) packages with PowerPAD™.

The THS3096 is offered in the 8-pin SOIC (D) and

the 14-pin TSSOP (PWP) packages with PowerPAD.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

PAGE 1
THS3092 THS3096 www.ti.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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THS3092 THS3096 www.ti.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted) TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C to 70°C -40°C to 85°C UNIT MIN/TYP/ MAX MHz TYP V/µs TYP ns TYP ns TYP dBc TYP AC PERFORMANCE Small-signal bandwidth, -3 dB G = 1, RF = 1.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted) TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE 25°C 25°C 0°C to 70°C -40°C to 85°C UNIT MIN/TYP/ MAX RL = 1 kΩ ±13.2 ±12.8 ±12.5 ±12.5 RL = 100 Ω ±12.5 ±12.1 ±11.8 ±11.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted) TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C to 70°C -40°C to 85°C UNIT MIN/TYP/ MAX MHz TYP V/µs TYP ns TYP ns TYP dBc TYP AC PERFORMANCE Small-signal bandwidth, -3 dB G = 1, RF = 1.
PAGE 7
THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted) TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE 25°C 25°C 0°C to 70°C -40°C to 85°C UNIT MIN/TYP/ MAX RL = 1 kΩ ±3.4 ±3.1 ±2.8 ±2.8 RL = 100 Ω ±3.1 ±2.7 ±2.5 ±2.
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THS3092 THS3096 www.ti.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TABLE OF GRAPHS FIGURE ±5-V graphs Noninverting frequency response 35 Inverting frequency response 36 0.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±15 V) (continued) 0.1 dB FLATNESS NONINVERTING FREQUENCY RESPONSE 16 Gain = 2, RF = 909 Ω, RL = 200 Ω, VO = 200 mVPP, VS = ±15 V 6.1 6 5.9 5.8 12 VO = 10VPP VO = 5VPP VO = 1VPP Gain = 5, RF = 715 Ω, RL = 100 Ω, VS = ±15 V 4 100 M 1G 1M Figure 6. FREQUENCY RESPONSE CAPACITIVE LOAD RECOMMENDED RISO vs CAPTIVATE LOAD 2ND HARMONIC DISTORTION vs FREQUENCY R(ISO) = 30.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±15 V) (continued) SLEW RATE vs OUTPUT VOLTAGE STEP SLEW RATE vs OUTPUT VOLTAGE STEP 4000 700 6000 Gain = 2 RL = 100 Ω RF = 909 Ω VS = ±15 V 3500 600 SR − Slew Rate − V/ µ s Rise Fall 500 400 300 Gain = 1 RL = 100 Ω RF = 1.1 kΩ VS = ±15 V 200 100 3000 2500 2000 Rise 1500 1000 0.5 1 1.5 2 2.5 3 3.5 1 2 3 4 5 6 7 8 9 10 0 10 12 14 16 18 20 Figure 15.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±15 V) (continued) INPUT OFFSET VOLTAGE vs CASE TEMPERATURE TRANSIMPEDANCE vs FREQUENCY 70 100 2.5 2 VS = ±15 V 1.5 1 VS = ±5 V 0.5 90 VS = ±15 V and ±5 V 70 60 50 40 30 10 10 0 1M 10 M 100 M 1G 100 k 1M 10 M 100 M 1G f − Frequency − Hz Figure 24. NONINVERTING SMALL SIGNAL TRANSIENT RESPONSE INVERTING LARGE SIGNAL TRANSIENT RESPONSE INVERTING LARGE SIGNAL TRANSIENT RESPONSE 6 0.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±15 V) (continued) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY CROSSTALK vs FREQUENCY 10 −10 G= 5, CH1 to 2 1 909 Ω 600 VS = ±15 V, RL = 100 Ω −20 Crosstalk − dB Closed-Loop Output Impedance − Ω Gain = 2, RISO = 5.11 Ω, RF = 909 Ω, VS = ±15 V Powerdown Quiescent Current - µ A 0 100 POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE 909 Ω 0.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±5 V) (continued) NONINVERTING FREQUENCY RESPONSE INVERTING FREQUENCY RESPONSE 16 16 1.25 VO = 2 VPP 12 10 VO = 1 VPP 8 VO = 5 VPP 6 G = 5, RF = 715 Ω, RL = 100 Ω, VS = ±5V 1M 10 8 VO = 2 VPP 4 G = 5, RF = 715 Ω, RL = 100 Ω, VS = ±5V 2 100 M 10 M 0 1G 0 1 2 3 5 6 7 8 9 SLEW RATE vs OUTPUT VOLTAGE STEP −40 G = 2, RF = 909 Ω, RL = 100 Ω −70 G =1, RF = 1.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (±5 V) (continued) INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 2 1.5 1 0.5 VS = ±5 V TA = -40 to 85°C 0 -0.5 -1 -1.5 -2 -2.5 -3 5 VS = ±5 V IIB- 6 5 IOS 4 3 2 IIB+ 1 0 -40 -30 -20 -10 0 -3.5 100 1000 Figure 47. 0.8 0.6 0.4 1 0.2 0 0 −1 −0.2 −2 −0.4 −3 −0.6 −4 −0.8 −1 0 10 20 30 40 50 60 70 80 90 0.2 0.4 0.6 0.8 1 t − Time − µs Figure 48. Figure 49.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 APPLICATION INFORMATION WIDEBAND, NONINVERTING OPERATION The THS3092/6 are unity gain stable 135-MHz current-feedback operational amplifiers, designed to operate from a ±5-V to ±15-V power supply. Figure 52 shows the THS3092 in a noninverting gain of 2-V/V configuration typically used to generate the performance curves.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 WIDEBAND, INVERTING OPERATION Figure 53 shows the THS3092 in a typical inverting gain configuration where the input and output impedances and signal gain from Figure 52 are retained in an inverting circuit configuration. +VS 50 Ω Source + VI 15 V +VS + 0.1 µF + VI RG RF 402 Ω RM 57.6 Ω 806 Ω 0.1 µF RG 909 Ω 6.8 µF +VS 2 + 50 Ω Source VI 57.6 Ω −15 V +VS 2 909 Ω RF VS RG _ 402 Ω RT + −VS Figure 53.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 20 V 10 V 0.01 F 4.99 k 1:1 330 pF 200 THS3092 24.9 *Hybrid Connection Not Shown For Simplicity 4.99 k Hybrid 0.022 F To RX 604 0.022 F 10 V 0.015 F THS3092 Figure 56. 100 − + 330 pF + 14.5 dBm Line Power 604 133 200 100 − DAC VIN− − 22 pF 1.21 k 14.5 dBm Line Power 6.8 F 49.9 + 22 pF DAC VIN− 604 THS3092 330 pF 1.21 k 0.01 F 22 pF 0.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 45 Gain = 5, VS = ±15 V Recommended R ISO − Ω 40 35 30 25 20 15 715 Ω 178 Ω 10 − RISO CL + 5 0 10 100 CL − Capacitive Load − pF Figure 58. Recommended RISO vs Capacitive Load Figure 61 shows another method used to maintain the low frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of RISO.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 rails and are given in the specification tables. Above the Enable Threshold Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. 715 Ω VS 178 Ω 5.11 Ω _ 24.9 Ω + −VS 715 Ω VS VS 178 Ω _ 24.9 Ω 1 nF 5.11 Ω + −VS Figure 63.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 and off are specified as the time it takes for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 • • Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them.
PAGE 23
THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 PowerPAD™ LAYOUT CONSIDERATIONS 1. PCB with a top side etch pattern as shown in Figure 67. There should be etch for the leads as well as etch for the thermal pad. 2. Place 13 holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 DESIGN TOOLS PD − Maximum Power Dissipation − W 4 ΤJ = 125°C Evaluation Fixtures, Application Support 3.5 θJA = 45.8°C/W 3 θJA = 95°C/W 2 1.5 1 0.5 θJA = 158°C/W 0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C Results are With No Air Flow and PCB Size = 3”x 3” θJA = 45.8°C/W for 8-Pin SOIC w/PowerPAD (DDA) θJA = 58.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 THS3092 EVM GND J8 -5V J7 5V J9 FB1 FB2 C1 C2 5V -5 V C3 + + C4 TP1 TP2 R6 J2 R1 5V U1:A R2 J3 2 3 R3 8 1 J1 R5 Figure 70. THS3092 EVM Board Layout (Top Layer) R4 4 -5 V J4 R7 R8 R9 6 5 7 R10 U1:B J5 J6 R11 R12 Figure 69. THS3092 EVM Schematic Figure 71.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 Figure 72. THS3092 EVM Board Layout (Power Plane) Figure 73. THS3092 EVM Board Layout (Bottom Layer) Table 3. THS3092 EVM Bill of Materials THS3092DGN EVM (1) 26 ITEM DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QTY MANUFACTURER'S PART NUMBER (1) 1 Bead, Ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 2 Cap. 22 µF, Tanatalum, 35 V, 10% D C1, C2 2 (AVX) TAJD685K035R 3 Cap. 0.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 THS3096 EVM GND J8 5V J7 -5 V J9 FB1 5V FB2 C5 + C1 C3 -5 V C2 C4 + TP1 TP2 R4 J1 R3 5V U1:A R1 J2 2 3 R2 14 4 R5 1 15 J3 Figure 75. THS3096 EVM Board Layout (Top Layer) R6 -5 V J4 R9 R8 R7 12 11 J5 R12 U1:B 13 9 6 R11 J6 R10 R13 J10 JP1 R14 5V R15 Figure 74. THS3096 EVM Schematic Figure 76.
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THS3092 THS3096 www.ti.com SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006 Figure 77. THS3096 EVM Board Layout (Power Plane) Figure 78. THS3096 EVM Board Layout (Bottom Layer) Table 4. THS3096 EVM Bill of Materials THS3096PWP EVM DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QTY MANUFACTURER'S PART NUMBER 1 Bead, Ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 2 Cap. 22 µF, Tanatalum, 25 V, 10% D C1, C2 2 (AVX) TAJD226K025R 3 Cap. 0.
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THS3092 THS3096 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS3092DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS3092DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.