Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Voltage feedback SOIC 8

IN−

IN+

THS4012

DORDGN

†

PACKAGE

(TOPVIEW)

1OUT

1IN−

1IN+

−V

CC+

2OUT

2IN−

2IN+

NULL

IN −

IN +

CC−

NULL

CC+

OUT

THS4011

D,DGN,ORJGPACKAGE

(TOPVIEW)

NC − Nointernalconnection

Cross-sectionviewshowing

PowerPADoption(DGN)

†

This packageisintheProductPreviewstageof

development. Pleasecontactyour localTIsalesof ficefor

availability.

192013 2

1312119 10

CC+

OUT

NULL

THS4011

FK PACKAGE

(TOPVIEW)

CC−

THS4011

THS4012

www.ti.com

SLOS216E –JUNE 1999–REVISED APRIL 2010

290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS

Check for Samples: THS4011, THS4012

FEATURES

• High Speed

– 290-MHz Bandwidth (G = 1, –3 dB)

– 310-V/ms Slew Rate

– 37-ns Settling Time (0.1%)

• Low Distortion

– THD = –80 dBc (f = 1 MHz, R

= 150 Ω)

• 110-mA Output Current Drive (Typical)

• 7.5-nV/√Hz Voltage Noise

• Excellent Video Performance

– 70-MHz Bandwidth (0.1 dB, G = 1)

– 0.006% Differential Gain Error

– 0.01° Differential Phase Error

• ±5-V to ±15-V Supply Voltage

• Available in Standard SOIC, MSOP

PowerPAD™, JG, or FK Packages

• Evaluation Module Available

DESCRIPTION

The THS4011 and THS4012 are high-speed,

single/dual, voltage feedback amplifiers ideal for a

wide range of applications. The devices offer good ac

performance, with 290-MHz bandwidth, 310-V/ms

slew rate, and 37-ns settling time (0.1%). These

amplifiers have a high output drive capability of 110

mA and draw only 7.8-mA supply current per

channel. For applications requiring low distortion, the

THS4011/4012 operate with a total harmonic

distortion (THD) of -80 dBc at f = 1 MHz. For video

applications, the THS4011/4012 offer 0.1-dB gain

flatness to 70 MHz, 0.006% differential gain error,

and 0.01° differential phase error.

RELATED DEVICES

DEVICE DESCRIPTION

THS4011/4012 290-MHz low-distortion high-speed amplifiers

THS4031/4032 100-MHz low-noise high-speed-amplifiers

THS4061/4062 180-MHz high-speed amplifiers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
THS4011 THS4012 www.ti.
PAGE 2
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 FUNCTIONAL BLOCK DIAGRAM Null 1 2 IN− 8 − 6 OUT 3 IN+ + Figure 1. THS4011 – Single Channel VCC 1IN− 2 − 8 1 1IN+ 2IN− 3 6 − 7 2IN+ 1OUT + 2OUT 5 + 4 −VCC Figure 2.
PAGE 4
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VCC Supply voltage ±16.
PAGE 5
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted) THS4011C/I THS4012C/I TEST CONDITIONS (1) PARAMETER UNIT TYP DYNAMIC PERFORMANCE BW 290 VCC = ±5 V 270 VCC = ±15 V 70 VCC = ±5 V 35 VCC = ±15 V, RL = 150 Ω VO(PP) = 20 V 4.
PAGE 6
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted) THS4011C/I THS4012C/I TEST CONDITIONS (1) PARAMETER MIN TYP 10 25 UNIT MAX DC PERFORMANCE VCC = ±15 V, VO = ±10 V, RL = 1 kΩ Open loop gain VCC = ±5 V, VO = ±2.
PAGE 7
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS (Continued) VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER THS4011M MIN TYP 160 (2) 200 UNIT MAX DYNAMIC PERFORMANCE Unit-gain bandwidth Closed loop, RL = 1 kΩ, VCC = ±15 V 70 VCC = ±5 V 35 VCC = ±2.5 V 30 VCC = ±15 V, RL = 150 Ω, VO(PP) = 20 V 2.5 VCC = ±5 V, RL = 150 Ω, VO(PP) = 20 V Bandwidth for 0.
PAGE 8
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) VCC = ±15 V, RL = 1 kΩ, TA = full range (unless otherwise noted) THS4011M TEST CONDITIONS (1) PARAMETER MIN TYP 6 14 5 10 MAX UNIT DC PERFORMANCE Open loop gain VIO VCC = ±15 V, VO = ±10 V, RL = 1 kΩ VCC = ±5 V, VO = ±2.
PAGE 9
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION 1.5 kΩ 1.5 kΩ 1.5 kΩ _ VI1 1.5 kΩ _ VO1 + CH1 VO2 150 Ω 150 Ω 50 Ω VI2 + CH2 50 Ω Figure 3. THS4012 Crosstalk Test Circuit TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 14 3 1.4 1 0.8 0.6 0.4 |VO | − Output Voltage Swing − V 1.
PAGE 10
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) CROSSTALK vs FREQUENCY 100 VCC = ±5 V VCC = ±15 V VCC = ±15 V −10 80 100 80 VCC = ±15 V 60 40 Open-Loop Gain − dB −20 −30 −40 −50 VI = CH2 VO = CH1 −60 VI = CH1 VO = CH2 −70 60 VCC = ±5 V 40 20 0 20 −80 0 1k 10k 100k 1M 10M −90 100k 100M 1M f − Frequency − Hz 100M −20 1k 1G 100K 10K 1M 10M Figure 11. Figure 12.
PAGE 11
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) NOISE SPECTRAL DENSITY vs FREQUENCY DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS 0.35° 100 Gain = 2 VCC = ±15 V RF = 1 kΩ 40 IRE-NTSC Modulation Worst-Case ±100 IRE Ramp Differential Phase Noise Spectral Density 0.3° 10 0.25° 0.2° 0.15° VCC = ±5 V 0.1° 0.05° VCC = ±15 V or ±5 V 1 10 100 1k 10k 0° 100k 1 2 f − Frequency − Hz Figure 19. DIFFERENTIAL GAIN vs NUMBER OF 150-Ω LOADS 0.
PAGE 12
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process, with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
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THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN− RG Figure 25. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹ ǒenǓ ) ǒIN ) 2 R Ǔ S 2 ǒ ) IN– ǒR F ø R G ǓǓ 2 ǒ ) 4 kTRs ) 4 kT R ø R F G Ǔ Where: k = Boltzmann's constant = 1.
PAGE 14
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 NF + www.ti.com ȱ ȡǒ Ǔ2 ǒ ȧ en ) IN ) ȧ ȧ Ȣ 10logȧ1 ) 4 kTR ȧ S ȧ Ȳ ȣȳ Ǔ S ȧȧ Ȥȧ ȧ ȧ ȧ ȴ 2 R Figure 26 shows the NF graph for the THS401x. NOISE FIGURE vs SOURCE RESISTANCE 30 f = 10 kHz TA = 25°C NF − Noise Figure − dB 25 20 15 10 5 0 10 k 100 1k Source Resistance − Ω 10 100 k Figure 26.
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THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 OFFSET NULLING The THS401x has low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4011/4012. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply (see Figure 28). VCC+ 0.1 µF + THS4011/4012 _ 10 kΩ 0.1 µF VCC − Figure 28.
PAGE 16
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com OFFSET VOLTAGE The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: Figure 29.
PAGE 17
THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.
PAGE 18
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
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THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 ǒ T P D + * T MAX A q JA Ǔ Where: PD = Maximum power dissipation of THS401x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) qJA = qJC + qCA qJC = Thermal coefficient from junction to case qCA = Thermal coefficient from case to ambient air (°C/W) Maximum Power Dissipation − W 3.5 DGN Package θJA = 58.4°C/W 2-oz Trace and Copper Pad With Solder 3 2.
PAGE 20
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.
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THS4011 THS4012 www.ti.com SLOS216E – JUNE 1999 – REVISED APRIL 2010 EVALUATION BOARD An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number SLOP230). This board has been configured for low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration.
PAGE 22
THS4011 THS4012 SLOS216E – JUNE 1999 – REVISED APRIL 2010 www.ti.com REVISION HISTORY Changes from Original (June 1999) to Revision A Page • Changed Feature List item From: 0.006% Differential Gain Error To: 0.01% Differential Gain Error .................................. 1 • Replaced the HIGH SPEED FAMILY of DEVICES table with the RELATED DEVICES table ............................................. 1 • Changed the Available Options table, THS4012ID MSOP Symbol From: TAIBG To: TIABZ ................
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS4011CDGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4011CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4011IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4011CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4011CDR SOIC D 8 2500 367.0 367.0 35.0 THS4011IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4012CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4012CDR SOIC D 8 2500 367.0 367.0 35.0 THS4012IDGNR MSOP-PowerPAD DGN 8 2500 358.
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MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.