Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Voltage feedback SOIC 8

THS4032

D AND DGN PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

−V

CC+

2OUT

2IN−

2IN+

NULL

IN−

IN+

CC−

NULL

CC+

OUT

THS4031

D, DGN, AND JG PACKAGE

(TOP VIEW)

NC − No internal connection

Cross-Section View Showing

PowerPAD Option (DGN)

192013 2

1312119 10

CC+

OUT

IN−

IN+

NULL

THS4031

FK PACKAGE

(TOP VIEW)

CC−

THS4031

THS4032

www.ti.com

SLOS224G –JULY 1999–REVISED MARCH 2010

100-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS

Check for Samples: THS4031, THS4032

FEATURES

• Ultralow 1.6 nV/√Hz Voltage Noise

• High Speed:

– 100-MHz Bandwidth [G = 2 (-1), –3 dB]

– 100-V/ms Slew Rate

• Very Low Distortion

– THD = –72 dBc (f = 1 MHz, R

= 150 Ω)

– THD = –90 dBc (f = 1 MHz, R

= 1 kΩ)

• Low 0.5-mV (Typ) Input Offset Voltage

• 90-mA Output Current Drive (Typical)

• ±5 V to ±15 V Typical Operation

• Available in Standard SOIC, MSOP

PowerPAD™, JG, or FK Package

• Evaluation Module Available

DESCRIPTION

The THS4031 and THS4032 are ultralow-voltage

noise, high-speed voltage feedback amplifiers that

are ideal for applications requiring low voltage noise,

including communications and imaging. The single

amplifier THS4031 and the dual amplifier THS4032

offer very good ac performance with 100-MHz

bandwidth (G = 2), 100-V/ms slew rate, and 60-ns

settling time (0.1%). The THS4031 and THS4032 are

unity gain stable with 275-MHz bandwidth. These

amplifiers have a high drive capability of 90 mA and

draw only 8.5-mA supply current per channel. With

–90 dBc of total harmonic distortion (THD) at f = 1

MHz and a very low noise of 1.6 nV/√Hz, the

THS4031 and THS4032 are ideally suited for

applications requiring low distortion and low noise

such as buffering analog-to-digital converters.

RELATED DEVICES

DEVICE DESCRIPTION

THS4051/2 70-MHz High-Speed Amplifiers

THS4081/2 175-MHz Low Power High-Speed Amplifiers

space

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 100-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS Check for Samples: THS4031, THS4032 FEATURES 1 The THS4031 and THS4032 are ultralow-voltage noise, high-speed voltage feedback amplifiers that are ideal for applications requiring low voltage noise, including communications and imaging.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 FUNCTIONAL BLOCK DIAGRAMS Null 2 IN− 3 IN+ VCC 1 1IN− 8 − 2 − 8 1 6 OUT 1IN+ + 2IN− 3 6 − 7 2IN+ 5 1OUT + 2OUT + 4 −VCC Figure 1. THS4031 – Single Channel Figure 2. THS4032 – Dual Channel ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted).
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN Dual supply VCC+ and VCC– Supply voltage MAX ±16 9 32 0 70 Single supply C-suffix Operating free-air temperature TA NOM ±4.5 I-suffix –40 85 M-suffix –55 125 UNIT V °C ELECTRICAL CHARACTERISTICS At TA = 25°C, VCC = ±15 V, and RL = 150 Ω (unless otherwise noted).
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = ±15 V, and RL = 150 Ω (unless otherwise noted). THS403xC, THS403xI TEST CONDITIONS (1) PARAMETER MIN TYP TA = 25°C 93 98 TA = full range 92 TA = 25°C 90 TA = full range 89 UNIT MAX DC PERFORMANCE VCC = ±15 V, RL = 1 kΩ, VO = ±10 V Open loop gain VCC = ±5 V, RL = 1 kΩ, VO = ±2.5 V TA = 25°C dB 95 0.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS At TA = full range, VCC = ±15 V, and RL = 1 kΩ (unless otherwise noted). THS403xC, THS403xI TEST CONDITIONS (1) PARAMETER MIN TYP 100 (2) 120 MAX UNIT DYNAMIC PERFORMANCE Unity gain bandwidth Small-signal bandwidth (–3 dB) BW Bandwidth for 0.1-dB flatness Full power bandwidth (3) SR Slew rate Settling time to 0.1% tS Settling time to 0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) At TA = full range, VCC = ±15 V, and RL = 1 kΩ (unless otherwise noted). THS403xC, THS403xI TEST CONDITIONS (1) PARAMETER MIN TYP VCC = ±15 V ±13.5 ±14.3 VCC = ±5 V ±3.8 ±4.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION 330 Ω 330 Ω 330 Ω _ VI1 330 Ω _ VO1 + CH1 150 Ω 50 Ω VO2 VI2 + CH2 150 Ω 50 Ω Figure 3. THS4032 Crosstalk Test Circuit Rg Rf Rg Rf VI _ VI + 50 Ω Submit Documentation Feedback _ VO + RL RL Figure 4. Step Response Test Circuit 8 50 Ω VO Figure 5.
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THS4031 THS4032 www.ti.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE DISTRIBUTION 14 250 Samples 3 Wafer Lots TA = 25°C VCC = ± 15 V 10 8 6 4 2 17.5 15 12.5 10 7.5 5 2.5 0 −2 0.4 0.8 −1.6 −1.2 −0.8 −0.4 0 VIO − Input Offset Voltage − mV 0 1.2 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 VIO − Input Offset Voltage − mV Figure 6. Figure 7. INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 0.8 1.2 3.10 −0.3 3.05 −0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE MAXIMUM OUTPUT VOLTAGE SWING vs FREE-AIR TEMPERATURE 14 VOM − Maximum Output Voltage Swing − ± V 14 |VO | – Output Voltage Swing – ± V TA = 25°C 12 RL = 1 KΩ 10 RL = 150 Ω 8 6 4 2 13 7 9 11 ± VCC – Supply Voltage – ± V 5 12 4.5 VCC = ± 5 V RL = 1 kΩ 4 3.5 VCC = ± 5 V RL = 150 Ω 3 −20 60 80 0 20 40 TA − Free-Air Temperature − °C Figure 11.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 15 VIC− Common-Mode Input − ± V 13 11 9 7 5 3 5 7 Gain = 1 RF = 1 kΩ PI = + 3 dBm Z O− Closed-Loop Output Impedance − Ω TA = 25°C 9 11 13 ± VCC − Supply Voltage − ± V 10 1 1 kΩ − 0.1 + 50 Ω VI THS403x 1000 VO Zo = −1 VI ( 0.
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THS4031 THS4032 www.ti.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) SLEW RATE vs FREE-AIR TEMPERATURE 0.1% SETTLING TIME vs OUTPUT VOLTAGE STEP SIZE 80 120 Gain = −1 RL = 150 Ω Vcc = ± 15 V Step = 20 V t s − 0.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SMALL SIGNAL FREQUENCY RESPONSE WITH VARYING FEEDBACK RESISTANCE 1 Output Amplitude − dB 0 VCC = ±15 V, RL = 150 W, 3 RF = 200 W VO(PP) = 200 mV, Gain = 1 −1 Output Amplitude (Large Signal) − dB 2 FREQUENCY RESPONSE WITH VARYING OUTPUT VOLTAGE SWING RF = 100 W RF = 50 W −2 RF = 0 W −3 −4 −5 2 1 VCC = +15 V, RL = 150 W, Gain = 1, RF = 0 W VO = 0.1 V(PP) 0 −1 −2 VO = 0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) SMALL SIGNAL FREQUENCY RESPONSE WITH VARYING FEEDBACK RESISTANCE FREQUENCY RESPONSE WITH VARYING OUTPUT VOLTAGE SWING 3 VCC = ±5 V, RF = 200 W Output Amplitude (Large Signal) − dB RL = 150 W, VO(PP) = 200 mV Gain = 1 RF = 100 W RF = 50 W RF = 0 W 2 1 VCC = 5 V, RL = 150 W, Gain = 1, RF = 0 W VO = 0.1 V(PP) 0 −1 VO = 0.2 V(PP) −2 VO = 0.4 V(PP) −3 VO = 0.8 V(PP) −4 VO = 1.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SMALL SIGNAL FREQUENCY RESPONSE WITH VARYING FEEDBACK RESISTANCE SMALL SIGNAL FREQUENCY RESPONSE WITH VARYING FEEDBACK RESISTANCE 2 2 1 RF = 1 kΩ 0 −1 Output Amplitude − dB Output Amplitude − dB 1 RF = 360 Ω RF = 100 Ω −2 −3 −4 −5 −6 VCC = ± 15 V Gain = −1 RL = 150 Ω VO(PP) = 0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 3 VCC = ± 15 V Gain = 2 RF = 300 Ω RL= 150 Ω −3 −6 0 VO − Output Voltage Level − dBv VO − Output Voltage Level − dBV 0 3 VI = 0.5 V RMS VI = 0.25 V RMS −9 −12 VI = 125 mV RMS −15 −18 VI = 62.5 mV RMS −3 −6 VI = 0.25 V RMS −9 −12 VI = 125 mV RMS −15 VI = 62.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS 0.2° 0.25° Gain = 2 RF = 680 Ω 40 IRE-NTSC Modulation Worst Case ± 100 IRE Ramp Gain = 2 RF = 680 Ω 40 IRE-PAL Modulation Worst Case ± 100 IRE Ramp VCC = ± 5 V 0.2° VCC = ± 5 V 0.1° Differential Phase Differential Phase 0.15° VCC = ± 15 V 0.15° VCC = ± 15 V 0.1° 0.05° 0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) 1-V STEP RESPONSE 1-V STEP RESPONSE 0.6 0.6 VCC = ± 15 V Gain = 2 RF = 300 Ω RL = 150 Ω See Figure 4 0.4 VO − Output Voltage − V VO − Output Voltage − V 0.4 VCC = ± 5 V Gain = 2 RF = 300 Ω RL = 150 Ω See Figure 4 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 t - Time - 200 ns/div t - Time - 200 ns/div Figure 47. Figure 48. 4-V STEP RESPONSE 20-V STEP RESPONSE 2.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The THS403x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high-performance amplifier that has wide bandwidth, high slew rate, fast settling time, and low distortion.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 NOISE CALCULATIONS AND NOISE FIGURE Noise can cause errors on very small signals. This is especially true when amplifying small signals.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com OPTIMIZING FREQUENCY RESPONSE Internal frequency compensation of the THS403x was selected to provide very wide bandwidth performance and still maintain a very low noise floor. In order to meet these performance requirements, the THS403x must have a minimum gain of 2 (–1). Because everything is referred to the noninverting terminal of an operational amplifier, the noise gain in a G = –1 configuration is the same as a G = 2 configuration.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 DRIVING A CAPACITIVE LOAD Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS403x has been internally compensated to maximize its bandwidth and slew-rate performance.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com OFFSET NULLING The THS403x has very low input offset voltage for a high speed amplifier. However, if additional correction is required, the designer can make use of an offset nulling function provided on the THS4031. By placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in Figure 56. VCC+ 0.1 mF 3 7 + THS4031 2 _ 4 8 1 10 k Ω 0.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 GENERAL CONFIGURATIONS When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer (see Figure 58). RG RF − VO + VI R1 C1 f V O + V I ǒ R 1) R F G Ǔǒ –3dB + 1 2pR1C1 Ǔ 1 1 ) sR1C1 Figure 58.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com CIRCUIT-LAYOUT CONSIDERATIONS In order to achieve the levels of high-frequency performance of the THS403x, it is essential that proper printed-circuit board (PCB) high-frequency design techniques be followed. A general set of guidelines is given below. In addition, a THS403x evaluation board is available to use as a guide for layout or for evaluating the device performance.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils) Figure 61. PowerPAD™ PCB Etch and Via Pattern 1. Prepare the PCB with a top-side etch pattern as shown in Figure 61. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com The actual thermal performance achieved with the THS403xDGN in its PowerPAD™ package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches (7,62 cm × 7,62 cm), then the expected thermal coefficient, qJA, is about 58.4°C/W. For comparison, the non-PowerPAD™ version of the THS403x IC (SOIC) is shown.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD™. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, qJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package.
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THS4031 THS4032 SLOS224G – JULY 1999 – REVISED MARCH 2010 www.ti.com EVALUATION BOARD An evaluation board is available for the THS4031 (literature number SLOP203) and THS4032 (literature number SLOP135). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 67. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration.
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THS4031 THS4032 www.ti.com SLOS224G – JULY 1999 – REVISED MARCH 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (September, 2008) to Revision G Page • Changed units for input voltage noise parameter (+25°C specifications) from nA/√Hz to nV√Hz ....................................... 4 • Changed units for input voltage noise parameter (full range of TA specifications) from nA/√Hz to nV√Hz ......................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) THS4032IDRG4 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) 4032I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS4031CDGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4031CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4031IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4031CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4031CDR SOIC D 8 2500 367.0 367.0 35.0 THS4031IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4031IDR SOIC D 8 2500 367.0 367.0 35.0 THS4032CDR SOIC D 8 2500 367.0 367.0 35.0 THS4032IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.
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MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.