Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Voltage feedback SOIC 8

FEATURES

D High Speed:

− 70 MHz Bandwidth (G = 1, −3 dB)

− 240 V/µs Slew Rate

− 60-ns Settling Time (0.1%)

D High Output Drive, I

= 100 mA (typ)

D Excellent Video Performance:

− 0.1 dB Bandwidth of 30 MHz (G = 1)

− 0.01% Differential Gain

− 0.01° Differential Phase

D Very Low Distortion:

− THD = −82 dBc (f = 1 MHz, R

= 150 Ω)

− THD = −89 dBc (f = 1 MHz, R

= 1 kΩ)

D Wide Range of Power Supplies:

− V

= ±5 V to ±15 V

D Available in Standard SOIC, MSOP

PowerPAD, JG, or FK Packages

D Evaluation Module Available

DESCRIPTION

The THS4051 and THS4052 are general-purpose,

single/dual, high-speed voltage feedback amplifiers ideal

for a wide range of applications including video,

communication, and imaging. The devices offer very good

ac performance with 70-MHz bandwidth, 240-V/µs slew

rate, and 60-ns settling time (0.1%). The THS4051/2 are

stable at all gains for both inverting and non-

inverting configurations. These amplifiers have a high

output drive capability of 100 mA and draw only 8.5-mA

supply current per channel. Excellent professional video

results can be obtained with the low differential gain/phase

errors of 0.01%/ 0.01° and wide 0.1-dB flatness to 30 MHz.

For applications requiring low distortion, the THS4051/2 is

ideally suited with total harmonic distortion of −82 dBc at

1 MHz.

RELATED DEVICES

DEVICE DESCRIPTION

THS4011/2

THS4031/2

THS4081/2

290-MHz Low Distortion High-Speed Amplifiers

100-MHz Low Noise High-Speed Amplifiers

175-MHz Low Power High-Speed Amplifiers

THS4052

D AND DGN

†

PACKAGES

(TOP VIEW)

1OUT

1IN−

1IN+

−V

CC+

2OUT

2IN−

2IN+

NULL

IN−

IN+

CC−

NULL

CC+

OUT

THS4051

D, DGN, AND JG PACKAGES

(TOP VIEW)

NC − No internal connection

Cross Section View Showing

PowerPAD Option (DGN)

†

This device is in the Product Preview stage of development.

Please contact your local TI sales office for availability.

1920132

1312119 10

CC+

OUT

IN−

IN+

NULL

THS4051

FK PACKAGE

(TOP VIEW)

CC−





SLOS238D − MAY 1999 − REVISED AUGUST 2008

  

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www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

DLP is a registered trademark of Texas Instruments. SMBus is a trademark of Intel Corp.

All other trademarks are the property of their respective owners.

Summary of content (36 pages)

PAGE 1
SLOS238D − MAY 1999 − REVISED AUGUST 2008 THS4051 D, DGN, AND JG PACKAGES (TOP VIEW) FEATURES D High Speed: − 70 MHz Bandwidth (G = 1, −3 dB) − 240 V/µs Slew Rate − 60-ns Settling Time (0.1%) NULL IN− IN+ VCC− D High Output Drive, IO = 100 mA (typ) D Excellent Video Performance: 1OUT 1IN− 1IN+ −VCC 1 8 2 7 3 6 4 5 VCC+ 2OUT 2IN− 2IN+ Cross Section View Showing PowerPAD Option (DGN) † This device is in the Product Preview stage of development.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)(1) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . .
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS AT TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) dynamic performance MIN TYP VCC = ±15 V VCC = ±5 V Gain = 1 VCC = ±15 V VCC = ±5 V Gain = 2 Bandwidth for 0.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) dc performance PARAMETER THS405xC, THS405xI TEST CONDITIONS† TYP 9 VCC = ±15 V, RL = 1 kΩ VO = ±10 V TA = 25°C TA = full range 5 VCC = ±5 V, RL = 250 Ω VO = ±2.5 V TA = 25°C TA = full range 2.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) power supply PARAMETER VCC ICC PSRR Supply voltage operating range THS405xC, THS405xI TEST CONDITIONS† MIN MAX Dual supply ±4.5 ±16.5 Single supply 9 33 VCC = ±15 V TA = 25°C TA = full range 8.5 VCC = ±5 V TA = 25°C TA = full range 7.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted) (continued) output characteristics TEST CONDITIONS† PARAMETER VO Output voltage swing VCC = ±15 V VCC = ±5 V RL = 250 Ω RL = 150 Ω VCC = ±15 V VCC = ±5 V RL = 1 kΩ VCC = ±15 V, TA = 25°C IO Output current‡ ISC Short-circuit current‡ VCC = ±15 V, TA = full range RL = 20 Ω VCC = ±5 V VCC = ±15 V THS4051M MIN TYP ±12 ±13 ±3.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE IB Input Bias Current − µ A 2.7 I 2.3 VCC = ± 5 V −1.5 −2.0 −2.5 VCC = ± 15 V −3.0 −3.5 −40 −20 0 20 40 60 80 TA - Free-Air Temperature - °C 2.6 2.5 2.4 7 9 11 13 ±VCC - Supply Voltage - V 15 Figure 5 SUPPLY CURRENT vs SUPPLY VOLTAGE 11 13.5 11 9 7 10 13 VCC = ± 15 V RL = 250 Ω VCC = ± 15 V RL = 1 kΩ 12.5 12 4.5 VCC = ± 5 V RL = 1 kΩ 4 3.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY OPEN LOOP GAIN AND PHASE RESPONSE vs FREQUENCY −20 30 VCC = ± 5 V & ±15 V 80 −40 Open Loop Gain − dB Crosstalk − dB 100 −50 −60 −70 0 Gain 60 −30 40 Gain −60 20 −90 Phase 0 −80 100k 1M 10M 100M −120 −20 f − Frequency − Hz 1k Figure 12 Phase VCC = ± 15 V Gain = 2 RF = 3.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY DISTORTION vs FREQUENCY −70 2nd Harmonic −80 3rd Harmonic 0 −1 −3 RF = 0 Ω −90 −5 −100 10M VCC = ± 15 V Gain = 1 RL = 150 Ω VO(PP) = 62 mV −6 100k 100M f − Frequency − Hz Figure 20 0.2 0.3 RF = 750 Ω Output Amplitude − dB Output Amplitude − dB 0.3 0.1 −0.0 −0.1 RF = 620 Ω −0.2 RF = 0 Ω −0.3 −0.4 100k 0.2 6.3 RF = 3.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 2 CL= 10 pF 1 6 Output Amplitude − dB 5 RL = 1 kΩ 4 RL = 150 Ω 3 2 VCC = ±15 V Gain = 2 RL = 2.7 k Ω VO(PP) = 125 mV 1 0 100k 0 −1 RF = 3.9 kΩ −2 RF = 1 kΩ −3 VCC = ± 15 V Gain = −1 RL = 150 Ω VO(PP) = 62 mV −4 −5 1M 10M f - Frequency - Hz −6 100k 100M Figure 29 VO(PP)=0.4 V −10 −20 VCC = ± 15 V Gain = 2 RF = 2.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS 1-V STEP RESPONSE 5-V STEP RESPONSE −0.0 −0.2 −0.4 0.6 2 0.4 1 0 −1 VCC = ± 5 V Gain = −1 RF = 3.9 kΩ RL = 150 Ω −2 −0.6 50 100 150 200 250 300 350 400 t - Time - ns VCC = ± 15 V Gain = 2 RF = 2.7 kΩ RL = 150 Ω 0.2 −0.0 −0.2 −0.4 −3 0 −0.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION THEORY OF OPERATION bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 42. The THS405x is a high-speed operational amplifier configured in a voltage feedback architecture.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) RS eRs en eni IN+ IN− Figure 43. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹ ǒenǓ ) ǒIN ) 2 R Ǔ S 2 ǒ ) IN– ǒR F ø R G ǓǓ 2 ǒ ) 4 kTRs ) 4 kT R ø R F G Ǔ Where: k = Boltzmann’s constant = 1.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION DRIVING A CAPACITIVE LOAD Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and slew rate performance.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION OFFSET VOLTAGE The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG +IIB− − − +IIB+ V OO +V IO ǒ 1) R R VO + RS F G Ǔ "I IB) R + VIO S ǒ 1) R R F G Ǔ "I IB* R F Figure 47.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL CONFIGURATIONS When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 49). RG RF − + VI R1 C1 f –3dB + Figure 49. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION CIRCUIT LAYOUT CONSIDERATIONS To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation board is available to use as a guide for layout or for evaluating the device performance.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) DIE Side View (a) Thermal Pad DIE End View (b) NOTE A: Bottom View (c) The thermal pad is electrically isolated from all terminals in the package. Figure 51. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches (or 76.2 mm × 76.2 mm), then the expected thermal coefficient, θJA, is about 58.4°C/W.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially devices with multiple amplifiers.
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www.ti.com SLOS238D − MAY 1999 − REVISED AUGUST 2008 APPLICATION INFORMATION EVALUATION BOARD An evaluation board is available for the THS4051 (literature number SLOP220) and THS4052 (literature number SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 58.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS4051CDGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4051IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4051CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4051CDR SOIC D 8 2500 367.0 367.0 35.0 THS4051IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4051IDR SOIC D 8 2500 367.0 367.0 35.0 THS4052CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4052CDR SOIC D 8 2500 367.0 367.0 35.
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