Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Voltage feedback VSSOP 8

DGK-8DGN-8 D-8 DRB-8

249 Ω

+5 V

49.9 Ω

-5 V

50 Ω Source

Low-Noise, Low-Distortion, Wideband Application Circuit

NOTE: Power supply decoupling capacitors not shown

249 Ω

50 Ω

THS4271

IN−

IN+

S−

OUT

THS4271

−100

−90

−80

−70

−60

−50

−40

1 10 100

Gain = 2

= 249 Ω

= 150 Ω

= 2 V

= ±5 V

Harmonic and Intermodulation Distortion − dB

HARMONIC AND INTERMODULATION

DISTORTION

FREQUENCY

f − Frequency − MHz

IMD

200 kHz Tone Spacing

= 2 V

Envelope

HD3

HD2

THS4271

THS4275

www.ti.com

SLOS397F –JULY 2002–REVISED OCTOBER 2009

LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE

VOLTAGE FEEDBACK AMPLIFIER

Check for Samples: THS4271 THS4275

FEATURES

DESCRIPTION

• Unity Gain Stability

• Low Voltage Noise

The THS4271 and THS4275 are low-noise, high slew

rate, unity gain stable voltage-feedback amplifiers

– 3 nV/√Hz

designed to run from supply voltages as low as 5 V

• High Slew Rate: 1000 V/μs

and as high as ±5 V. The THS4275 offers the same

• Low Distortion

performance as the THS4271 with the addition of a

power-down capability. The combination of low-noise,

– –92 dBc THD at 30 MHz

high slew rate, wide bandwidth, low distortion, and

• Wide Bandwidth: 1.4 GHz

unity gain stability make the THS4271 and THS4275

• Supply Voltages

high performance devices across multiple ac

specifications.

– +5 V, ±5 V

• Power Down Functionality (THS4275)

Designers using the THS4271 are rewarded with

higher dynamic range over a wider frequency band

• Evaluation Module Available

without the stability concerns of decompensated

amplifiers. The devices are available in SOIC, MSOP

APPLICATIONS

with PowerPAD™, and leadless MSOP with

• High Linearity ADC Preamplifier

PowerPAD™ packages.

• Wireless Communication Receivers

The THS4271 and THS4275 may have low-level

• Differential to Single-Ended Conversion

oscillation when the die temperature (also known as

• DAC Output Buffer

the junction temperature) exceeds +60°C. For more

• Active Filtering

information, see Maximum Die Temperature to

Prevent Oscillation.

RELATED DEVICES

DEVICE DESCRIPTION

THS4211 1-GHz voltage-feedback amplifier

THS4503 Wideband, fully-differential amplifier

THS3202 Dual, wideband current feedback amplifier

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (51 pages)

PAGE 1
DGN-8 DGK-8 D-8 THS4271 THS4275 DRB-8 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 LOW NOISE, HIGH SLEW RATE, UNITY GAIN STABLE VOLTAGE FEEDBACK AMPLIFIER Check for Samples: THS4271 THS4275 FEATURES 1 • • 23 • • • • • • DESCRIPTION Unity Gain Stability Low Voltage Noise – 3 nV/√Hz High Slew Rate: 1000 V/μs Low Distortion – –92 dBc THD at 30 MHz Wide Bandwidth: 1.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS Dual supply Supply voltage (VS+ and VS–) Single supply Input common-mode voltage range MIN MAX ±2.5 ±5 5 10 VS- + 1.4 VS+ – 1.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±5 V At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C (1) UNITS MIN/ TYP/ MAX AC PERFORMANCE G = 1, VO = 100 mVPP, RL = 150 Ω 1.4 GHz Typ G = –1, VO = 100 mVPP 400 MHz Typ G = 2, VO = 100 mVPP 390 MHz Typ G = 5, VO = 100 mVPP 85 MHz Typ G = 10, VO = 100 mVPP 40 MHz Typ 0.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued) At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE +25°C +25°C 0°C to +70°C –40°C to +85°C (1) UNITS MIN/ TYP/ MAX OUTPUT CHARACTERISTICS Output voltage swing G = +2 ±4 ±3.8 ±3.7 ±3.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: VS = 5 V At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C (1) UNITS MIN/ TYP/ MAX AC PERFORMANCE G = 1, VO = 100 mVPP, RL = 150 Ω 1.2 GHz Typ G = –1, VO = 100 mVPP 380 MHz Typ G = 2, VO = 100 mVPP 360 MHz Typ G = 5, VO = 100 mVPP 80 MHz Typ G = 10, VO = 100 mVPP 35 MHz Typ 0.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS: VS = 5 V (continued) At RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE +25°C +25°C 0°C to +70°C Specified operating voltage 5 10 10 Maximum quiescent current 20 22 25 (1) UNITS MIN/ TYP/ MAX 10 V Max 27 mA Max –40°C to +85°C POWER SUPPLY Minimum quiescent current 20 18 16 14 mA Min Power-supply rejection (+PSRR) VS+ = 5.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (±5 V) FIGURE Small-signal unity gain frequency response 1 Small-signal frequency response 2 0.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 Table of Graphs (5 V) FIGURE Small-signal unity gain frequency response 39 Small-signal frequency response 40 0.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.
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THS4271 THS4275 www.ti.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS: ±5 V (continued) DIFFERENTIAL GAIN vs NUMBER OF LOADS DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.015 Gain = 2 Rf = 1.3 kΩ VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.09 ° Differential Phase − 0.020 3 NTSC 0.010 0.08 0.07 Rising Edge 2 VO − Output Voltage − V Gain = 2 Rf = 1.3 kΩ VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.025 Differential Gain − % SETTLING TIME 0.
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THS4271 THS4275 www.ti.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS: ±5 V (continued) POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY Power-down Output Impedance − Ω 1M Gain = 1 RL = 150 Ω VIN = 1 dBm VS = ±5 V 100 k 10 k 100 1 100 k 1M 10 M 100 M f − Frequency − Hz 1G Figure 37. TYPICAL CHARACTERISTICS: 5 V SMALL-SIGNAL UNIT GAIN FREQUENCY RESPONSE SMALL-SIGNAL UNIT GAIN FREQUENCY RESPONSE 20 0 −1 −2 −3 −4 100 k 1M 0.
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THS4271 THS4275 www.ti.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS: 5 V (continued) THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY −70 −80 −90 −100 10 40 35 30 0 20 40 100 Hz 1k 10 k 100 k 1M 10 M 1 100 M f − Frequency − Hz Figure 54. Figure 55. Figure 56. SETTLING TIME QUIESCENT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE vs LOAD RESISTANCE 30 2 TA = 85°C Rising Edge 1.5 25 1 0 −0.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS: 5 V (continued) REJECTION RATIOS vs CASE TEMPERATURE 100 120 VS = 5 V 90 PSRR+ 70 PSRR− 60 CMRR 50 PSRR+ 100 PSRR− Rejection Ratios − dB 40 30 80 60 CMMR 40 20 20 VS = 5 V 10 0 10 k 100 k 1M 10 M f − Frequency − Hz 0 −40−30−20−100 10 20 30 40 50 60 70 80 90 100 M VS = 5 V 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 Input Common-Mode Voltage Range − V Figure 63. Figure 64. Figure 65.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS: 5 V (continued) POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY 1M TA = 85°C 1000 TA = 25°C 800 TA = −40°C 600 400 200 0 2.5 3 3.5 4 4.5 VS − Supply Voltage − ±V Figure 72. 18 Submit Documentation Feedback 5 6.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 APPLICATION INFORMATION MAXIMUM DIE TEMPERATURE TO PREVENT OSCILLATION The THS4271 and THS4275 may have low-level oscillation when the die temperature (also called junction temperature) exceeds +60°C. The oscillation is a result of the internal design of the bias circuit, and external configuration is not expected to mitigate or reduce the problem.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com HIGH-SPEED OPERATIONAL AMPLIFIERS WIDEBAND, NONINVERTING OPERATION The THS4271 and the THS4275 operational amplifiers set new performance levels, combining low distortion, high slew rates, low noise, and a unity-gain bandwidth in excess of 1 GHz. To achieve the full performance of the amplifier, careful attention must be paid to printed-circuit board (PCB) layout and component selection.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 WIDEBAND, INVERTING GAIN OPERATION Since the THS4271 and THS4275 are general-purpose, wideband voltage-feedback amplifiers, several familiar operational amplifier applications circuits are available to the designer. Figure 76 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 75 are retained in an inverting circuit configuration.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com SINGLE-SUPPLY OPERATION The THS4271 is designed to operate from a single 5-V to 15-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 77 demonstrate methods to configure an amplifier in a manner conducive for single-supply operation. +VS 50 Ω Source + VI 49.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 Table 3. Power-Down Threshold Voltage Levels (REF > MIDRAIL) SUPPLY VOLTAGE (V) REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) Floating or 5 ≥4 ≤ 3.3 2.5 ≥ 1.5 ≤ 0.8 1 ≥0 ≤ -0.7 Floating or 5 ≥ 3.3 ≤ 3.3 4 ≥3 ≤ 2.3 3.5 ≥ 2.5 ≤ 1.8 ±5 5 In Table 3, the threshold levels are derived by the following equations: REF - 1 V for enable REF - 1.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 50 Ω Source www.ti.com THS4271 +5 V + VI 49.9 Ω RT THS4271 _ -5 V 100 Ω ADS807 100 Ω 12-Bit, Rf 1.82 kΩ 249 Ω 100 Ω 249 Ω 14-Bit, 400 MSps 249 Ω 1 nF IF+ DAC5675 0.1 µF CF 1 nF CM 53 Msps IN 249 Ω Rg _ IN 68 pf 16.5 Ω + 3.3 V 3.3 V 0.1 µF RISO 249 Ω 49.9 Ω 249 Ω 49.9 Ω RF(out) IF1 nF 1 nF _ For best performance, high-speed ADCs should be driven differentially.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 A Low-Noise Receiver With the THS4271 THEORY AND GUIDELINES A combination of two THS4271 amplifiers can create a high-speed, low-distortion, low-noise differential receiver circuit as depicted in Figure 83. With both amplifiers operating in the noninverting mode of operation, the circuit presents a high load impedance to the source.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com Intercept points are specifications long used as key design criteria in the RF communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). Use of the intercept point, rather than strictly the intermodulation distortion, allows simpler system-level calculations.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 THS4271/THS4275 ENI + RS IBN ERS EO _ 4kTRS ERF Rf Rg 4kT Rg 4kTRf IBI 4kT = 1.6E-20J at 290K Figure 87. Noise Analysis Model The total output spot noise voltage can be computed as the square of all square output noise voltage contributors.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the THS4271 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 5. Socketing a high speed part like the THS4271 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4271 onto the board.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com where: PD = Maximum power dissipation of THS4271 (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to the case θCA = Thermal coefficient from the case to ambient air (°C/W). (6) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 Performance vs Package Options The THS4271 and THS4275 are offered in different package options. However, performance may be limited due to package parasitics and lead inductance in some packages. In order to achieve maximum performance of the THS4271 and THS4275, Texas Instruments recommends using the leadless MSOP (DRB) or MSOP (DGN) packages, in addition to proper high-speed PCB layout.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com The peaking in the frequency response is due to the lead inductance in the feedback path. Each pad and trace on a PCB has an inductance associated with it, which in conjunction with the inductance associated with the package may cause peaking in the frequency response, causing the device to become unstable. In order to achieve the maximum performance of the device, PCB layout is very critical.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 Figure 96. THS4271/THS4275 EVM Board Layout (Top Layer) Figure 98. THS4271/THS4275 EVM Board Layout (Third Layer, Power) Figure 97. THS4271/THS4275 EVM Board Layout (Second Layer, Ground) Figure 99.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com Vs+ 7 8 2 _ U1 R6 6 J4 Vout 3 + R7 4 1 J2 Vin+ Vs − R4 J7 VS− J6 GND J5 VS+ TP1 FB1 FB2 VS− C5 C6 VS+ C1 C2 + + C3 C4 Figure 100. THS4271 Unity Gain EVM Circuit Configuration Figure 102. THS4271 Unity Gain EVM Board Layout (Second Layer, Ground) Figure 101. THS4271 Unity Gain EVM Board Layout (Top Layer) Figure 103.
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THS4271 THS4275 www.ti.com SLOS397F – JULY 2002 – REVISED OCTOBER 2009 Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4271 is available through either the Texas Instruments web site (www.ti.
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THS4271 THS4275 SLOS397F – JULY 2002 – REVISED OCTOBER 2009 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January, 2004) to Revision F Page • Updated document format to meet current standards ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) THS4275DRBTG4 Package Type Package Pins Package Drawing Qty ACTIVE SON DRB 8 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -40 to 85 4275 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing THS4271DGNR MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4271DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4271DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4271DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4271DR SOIC D 8 2500 367.0 367.0 35.0 THS4271DRBT SON DRB 8 250 210.0 185.0 35.0 THS4275DRBT SON DRB 8 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.