Datasheet

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ADS807
12-Bit,
53 Msps
R
ISO
0.1 µF
16.5 Ω
68 pf
0.1 µF
IN
IN
CM
1.82 kΩ
_
+
THS4302
R
f
49.9 Ω
V
I
+
22 µF 47 pF 0.1 µF
V
S+
50-Ω Source
R
g
30.1 Ω
FB
FB = Ferrite Bead
*2.5 V
*2.5 V
* = Low Impedance
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
10 M 100 M 1 G
1
f - Frequency - Hz
Normalized Gain - dB
R
(ISO)
= 12.1 Ω,
C
L
= 47 pF
V
S
= 5 V
R
(ISO)
= 8 Ω,
C
L
= 100 pF
R
(ISO)
= 24.9 Ω,
C
L
= 10 pF
Power Supply Decoupling Techniques and
Driving Capacitive Loads
THS4302
SLOS403H – OCTOBER 2002 – REVISED AUGUST 2006
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4302. Long PC board traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4302 output pin (see Board Layout
Guidelines).
The criterion for setting this R
(ISO)
resistor is a
maximum bandwidth, flat frequency response at the
load.
For best performance, high-speed ADCs
should be driven differentially. See the
THS4500 family of devices for more
information.
Figure 47. Driving an ADC With a Single-Ended
Figure 48. Driving Capacitive Loads
Input
Recommendations
One of the most demanding, and yet very common,
Power supply decoupling is a critical aspect of any
load conditions for an op amp is capacitive loading.
high-performance amplifier design process. Careful
Often, the capacitive load is the input of an A/D
decoupling provides higher quality ac performance
converter, including additional external capacitance,
(most notably improved distortion performance). The
which may be recommended to improve A/D linearity.
following guidelines ensure the highest level of
High-speed amplifiers like the THS4302 can be
performance.
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
1. Place decoupling capacitors as close to the
directly on the output pin. When the amplifier's
power supply inputs as possible, with the goal of
open-loop output resistance is considered, this
minimizing the inductance of the path from
capacitive load introduces an additional pole in the
ground to the power supply. Inductance in series
signal path that can decrease the phase margin.
with the bypass capacitors will degrade
When the primary considerations are frequency
performance. Note that a narrow lead or trace
response flatness, pulse response fidelity, or
has about 0.8 nH of inductance for every
distortion, the simplest and most effective solution is
millimeter of length. Each printed-circuit board
to isolate the capacitive load from the feedback loop
(PCB) via also has between 0.3 and 0.8 nH
by
depending on length and diameter. For these
inserting a series isolation resistor between the
reasons, it is recommended to use a power
amplifier output and the capacitive load.
supply trace about the width of the package for
each power supply lead to the capacitors, and 3
or more vias to connect the capacitors to the
ground plane.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Solid power planes can lead to PCB resonances
14 Submit Documentation Feedback Copyright © 2002 – 2006, Texas Instruments Incorporated
Product Folder Link(s): THS4302