Datasheet

www.ti.com
R1
49.9 Ω
_
+
R
f
V
I
R
g
8
7
6
5
R2
49.9 W
R3
*
J2
V
O
U1
1 2 3 4
+
22 mF
NC
C3
FB1
*
C7
47pF
C8
C5
0.1 mF
R4
30.1 W
11 10 912
J4
V
S-
+
22 Fm
*
C6
47pF
C9
C4
0.1 mF
R5
30.1 W
FB2
V
S+
J3
14
13
16
PD
1 mF
C1
J1
J6
*=Notpopulated
C2
THS4302
SLOS403H – OCTOBER 2002 – REVISED AUGUST 2006
Figure 52. Typical THS4302 EVM Circuit Configuration
Figure 53. THS4302EVM Layout Figure 54. THS4302EVM Figure 55. THS4302EVM
(Top Layer and Silkscreen Layer) Board Layout Board Layout
(Ground Layers 2 and 3) (Bottom Layer)
Copyright © 2002 – 2006, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4302