Datasheet

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THS8135

www.ti.com

SLAS343B –MAY 2001–REVISED APRIL 2013

10-BIT 240-MSPS VIDEO DAC

WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601)-COMPLIANT FULL-SCALE RANGE

Check for Samples: THS8135

FEATURES

• Triple 10-Bit D/A Converters

• Bi-Level (EIA) or Tri-Level (SMPTE) Sync

Generation

• 240-MSPS Operation

• Integrated Sync-On-Green/Luminance or Sync-

• YPbPr/RGB Configurable Blanking Levels,

On-All Composite Sync Insertion

Correctly Positioned for Either Full (0-1023) or

Video (ITU-R.BT601) Compliant Input Code • Internal Voltage Reference

Ranges

• Low-Power Operation From 3.3-V Analog and

• Generic Triple DAC Mode for Non-Video 1.8-V Digital Suply Levels

Applications

APPLICATIONS

• Direct Drive of Double-Terminated 75-Ω Load

Into Standard Video Levels

• High-Definition Television (HDTV) Set-Top

Boxes/Receivers/Displays

• 3x10 Bit 4:4:4, 2x10 Bit 4:2:2 or 1x10 Bit 4:2:2

(ITU-R.BT656) Multiplexed YCbCr/GBR Input

• High-Resolution Image Processing

Data Formats

DESCRIPTION

The THS8135 is a general-purpose triple high-speed D/A converter optimized for use in video/graphics

applications. The device operates from 3.3-V analog and 1.8-V digital supplies. The THS8135 performance is

assured at a sampling rate up to 240 MSPS. The THS8135 consists of three 10-bit D/A converters and additional

circuitry for bi-level/tri-level sync and blanking level generation. By providing a dc offset for the lowest video

amplitude output in video DAC mode, the device can insert a (negative) bi-level or (negative/positive) tri-level

sync on either only the green/luminance (sync-on-green/sync-on-Y) channel or on all channels for video

applications. A generic DAC mode avoids this dc offset, making this device suitable for non-video applications as

well.

The THS8135 is a footprint-compatible functional upgrade to the THS8133. In addition, the THS8135 allows a

higher update rate for oversampled video digitizing for all PC graphics formats up to UXGA (1600x1200)

resolution at 85 Hz and all practical digital TV formats including HDTV. The support for oversampling significantly

reduces the complexity of the analog reconstruction filter required behind the DAC.

Standard video levels can be generated for the full 10-bit input code range. Alternatively, the same levels can be

reached from a reduced input code range compliant to the video sampling standard ITU-R.BT-601. In that case,

the full-scale range of the DAC is dependent on the RGB or YCbCr color space configuration of the device.

When configured for RGB operation, full video output swing is reached for input codes 64-940 on all channels.

When configured for YCbCr operation, code range 64-940 on Y and code range 64-960 on Cb and Cr channels

generate full output swing using internal amplitude scaling on these color components. The device provides

headroom to accommodate under-/over-shoot outside the ITU-R.BT601 range to allow the generation of ITU-

R.BT601 illegal colors or super-black / super-white levels.

A digital control input for insertion of a reference (blanking) level on the analog outputs is included. The

amplitude of the blanking level is configurable for either RGB or YPbPr component outputs and for full or reduced

input code ranges. The inserted sync output amplitude(s) always has the required 7:3 ratio to the full-scale video

amplitude.

The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device

provides a flexible configuration of maximum output current drive. The devices output drivers have been

specifically designed to produce standard video output levels when directly connected to a single-ended double-

terminated 75-Ω coaxial cable.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 10-BIT 240-MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601)-COMPLIANT FULL-SCALE RANGE Check for Samples: THS8135 FEATURES 1 • • • 2 • • • Triple 10-Bit D/A Converters 240-MSPS Operation YPbPr/RGB Configurable Blanking Levels, Correctly Positioned for Either Full (0-1023) or Video (ITU-R.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com The input data format can be either 3x10 bit 4:4:4, 2x10 bit 4:2:2, or 1x10 bit 4:2:2. This enables a direct interface to a wide range of video DSP/ASICs including parts generating ITU-R.BT656 formatted output data. However, the THS8135 needs specific input synchronization signals to properly insert a composite sync onto its outputs as it does not extract embedded SAV/EAV synchronization codes from the ITU-R.BT656 input.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 Functional Block Diagram DVDD DVSS COMP FSADJ VREF Bandgap Reference RCr[9:0] Input Formatter GY[9:0] BCb[9:0] CLK M1 M2 R/Cr Register DAC ARPr G/Y Register DAC AGY B/Cb Register DAC ABPb Configuration Control SYNC/BLANK Control BLANK SYNC SYNC_T AVDD AVSS Table 2. Terminal Functions TERMINAL NAME NO.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION DVSS 11 I Digital ground FSADJ 38 I Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of a resistor RFS connected between this terminal and AVSS. Figure 5 shows the relationship between full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 Ω.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 DETAILED DESCRIPTION The THS8135 is a fast well-matched triple DAC with current outputs optimized for video applications without sacrificing its usefulness as a general-purpose triple DAC, thanks to a generic DAC mode. For video applications, the device can embed an analog output (composite) bi-level or tri-level sync on only the green/luma channel or on all three DAC output channels.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Table 3. Video vs Generic Mode Selection SYNC BLANK SYNC_T 1 1 1 Generic DAC mode. Blanking override inactive. OPERATION MODE AND DAC OUTPUT 1 0 1 Generic DAC mode. Blanking override active. Blanking level position is according to the codes of Table 7, however no dc bias is present on the Y, R, G, and B outputs 1 1 0 Video DAC mode. Blanking override inactive 1 0 0 Video DAC mode. Blanking override active.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 Selection of Color Space and Input Formatter Configuration (Available in Video DAC and Generic DAC Modes) Input data to the device can be supplied from a 3x10b GBR or YCbCr input port. If the device is configured to take data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at the full clock speed of CLK.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Table 7. Full-Scale or ITU.BT601 Reduced-Scale Mode Selection and Impact on Blanking Level Positioning M1_INT L M2_INT L BLNK_INT AVAILABLE IN VIDEO DAC (V) AND GENERIC DAC (G) MODES? L CHANNEL OUTPUT LEVEL DURING BLANK ACTIVE CORRESPONDING TO DAC INPUT CODE: OPERATION MODE AGY ABPb ARPr V, G GBR 3x10b 4:4:4, full scale range 0 0 0 GBR 3x10b 4:4:4, ITU-R.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 Figure 1 through Figure 4 show the nominal output voltage levels for full- or reduced-range input code range configurations on R, G, B, and Y versus Cb and Cr channels. Note that in full-scale input code range configuration, the blanking level is at 350 mV on all outputs; while in reduced-scale operation it is at 400 mV on all outputs.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Input Codes Super-Black/Super-White Excursions (Reduced-Scale Input Code Range) VO mV 1023 940 1167 1100 64 0 400 350 700 mV 817 mV 300 mV 300 mV 100 NOTE: Choose RFS for 700 mV from input codes 64−940 on Y. Figure 3. YRGB Outputs, Reduced-Scale Input Code Range Input Codes Illegal Color Difference Outputs VO mV 1023 960 800 700 512 400 64 0 50 0 800 mV 300 mV 700 mV 300 mV 0 Figure 4.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 1450 Full-Scale DAC Output Current Adjustment at 37.5-Ω DAC Termination 1350 VO − Output Voltage − mV 1250 1150 1050 950 850 750 650 550 450 350 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 7.3 R(FS) − Full-Scale Resistance − kΩ Figure 5.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com DAC Outputs The position of the blanking levels in the THS8135 differs from the position of the blanking levels in the THS8133. This is to accommodate both full- and reduced-scale configurations on this device, while the THS8133 only supported full-scale. When the DAC output is ac-coupled, as is typically the case, there is no change to the output video waveform.
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THS8135 www.ti.com CLK SLAS343B – MAY 2001 – REVISED APRIL 2013 T0 T1 T2 T3 T4 T5 T6 T7 T8 RCr(0) RCr(1) RCr(2) RCr(3) RCr(4) RCr(5) RCr(6) RCr(7) RCr(8) GY(0) GY(1) GY(2) GY(3) GY(4) GY(5) GY(6) GY(7) GY(8) BCb(0) BCb(1) BCb(2) BCb(3) BCb(4) BCb(5) BCb(6) BCb(7) BCb(8) Data Path Latency = 7.5 CLK Cycles RCr(0), GY(0), BCb(0) Registered ARPr, AGY, ABPb Output Corresponding to RCr(0), GY(0), BCb(0) Figure 7.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Figure 10 shows how to control the SYNC, SYNC_T, and BLANK signals to generate tri-level sync levels and blanking at the DAC output in video mode. A bi-level (negative) sync can be generated similarly by avoiding the positive transition on SYNC_T during SYNC low. Note that on the THS8135 it is required to keep SYNC_T low outside the sync interval to avoid entering the generic DAC mode.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage Supply voltage, difference between analog and digital supplies AVDD to AVSS -0.5 V to 3.6 V DVDD to DVSS -0.5 V to 2 V AVDD to DVDD, AVSS to DVSS -0.5 to 0.5 V Digital input voltage range to DVSS TA Operating free-air temperature range Tstg Storage temperature range (1) -0.5 V to DVDD + 0.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com Electrical Characteristics over recommended operating conditions with fCLK = 240 MSPS and use of internal reference voltage VREF, with RFS = RFS(nom) and 37.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 Analog (DAC) Outputs PARAMETER TEST CONDITIONS MIN DAC resolution INL Integral nonlinearity Differential nonlinearity PSRR Power supply ripple rejection ratio of DAC output (full scale) XTALK Crosstalk between channels (2) Vrefo Voltage reference output RR VREF output resistance KIMBAL Imbalance between DACs -1.1/0.9 -2/1.5 Static, best-fit, sync-on-all, video mode, RGB ITU.R-BT601 -1.2/0.8 -2/1.5 -1.61/0.94 -2/1.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com 400 390 380 P − Power − mW 370 360 350 340 330 320 310 300 0 50 100 150 200 250 300 f − Frequency − MHz Figure 11. Power vs Clock Frequency, RGB Mode, 1-MHz Input Tone on All Channels 600 P − Power − mW 500 400 300 200 100 0 0 50 100 150 200 250 300 f − Frequency − MHz Figure 12. Power vs Clock Frequency, Generic DAC Mode 1.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 0.5 DNL − Differential Nonlinearity − LSB 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 1 76 151 226 301 376 451 526 601 676 751 826 901 976 1051 Input Code Figure 13. DNL, Generic DAC Mode (1.3-V Output Compliance) 1.5 INL − Integral Nonlinearity − LSB 1.0 0.5 0.0 −0.5 −1.0 −1.5 1 103 205 307 409 511 613 715 817 919 1021 Input Code Figure 14. Best-Fit INL, Generic DAC Mode (1.
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THS8135 SLAS343B – MAY 2001 – REVISED APRIL 2013 www.ti.com 0 −1 Amplitude − dB −2 −3 −4 −5 −6 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 f − Frequency − MHz Figure 15.
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THS8135 www.ti.com SLAS343B – MAY 2001 – REVISED APRIL 2013 REVISION HISTORY Revision SLAS343B Comments Added Thermal Specifications.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.