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THS8200

All-Format Oversampled Component Video/PC Graphics

D/A System With Three 11-Bit DACs, CGMS Data Insertion

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SLES032D

June 2002–Revised June 2013

Summary of content (102 pages)

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THS8200 All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Contents 1 Introduction 1.1 1.2 1.3 1.4 2 Terminal Descriptions 2.1 2.2 3 4.6 4.7 2 ........................................................................................................ 10 .......................................................................................................... 13 Data Manager (DMAN) ................................................................................................... 3.1.
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THS8200 www.ti.com 4.8 4.9 4.10 4.11 4.12 5 5.3 59 64 64 65 67 68 69 71 72 74 77 77 77 77 78 78 78 79 ...................................................................................................... 80 Video vs Computer Graphics Application .............................................................................. 80 DVI to Analog YPbPr/RGB Application ................................................................................. 81 Master vs Slave Timing Modes ..........................
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 7.7.3 7.8 7.9 7.10 7.11 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels .................................................. 7.7.4 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels .................................................. Nonlinearity ........................
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 List of Figures 3-1 Functional Block Diagram ....................................................................................................... 13 4-1 24-/30-Bit RGB or YCbCr Data Format 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 6-1 6-2 6-3 .......................................
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 6-4 Master Operation Mode of THS8200 .......................................................................................... 82 7-1 Power vs Frequency ............................................................................................................. 87 7-2 Power vs Frequency ............................................................................................................. 88 7-3 Power vs Frequency .................
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 List of Tables .............................................................................................................. 2-1 Terminal Functions 4-1 Supported Input Formats ........................................................................................................ 17 5-1 I2C Register Map .................................................................................................................
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion Check for Samples: THS8200 1 Introduction 1.
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THS8200 www.ti.com 1.2 • • • • • SLES032D – JUNE 2002 – REVISED JUNE 2013 Applications DVD Players Digital-TV/Interactive-TV/Internet Set-Top Boxes Personal Video Recorders HDTV Display or Projection Systems Digital Video Systems 1.3 Description THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and settop boxes, or any system requiring the conversion of digital component video signals into the analog domain.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 2 Terminal Descriptions 2.1 Pinout www.ti.com RESETB DVDD DVSS GY0 GY1 GY2 GY3 GY4 GY5 GY6 GY7 GY8 GY9 FID VDD_IO GND_IO VS_IN HS_IN RCr0 RCr1 PFP PACKAGE (TOP VIEW) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 464544 HS_OUT VS_OUT SDA SCL DO9 DO8 DO7 DO6 DO5 VDD_IO D1CLKO GND_IO DO4 DO3 DO2 DO1 DO0 DVSS DVDD N.C.
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THS8200 www.ti.com 2.2 SLES032D – JUNE 2002 – REVISED JUNE 2013 Terminal Functions Table 2-1. Terminal Functions TERMINAL I/O (1) DESCRIPTION NAME NO. ABPb 15 O Analog output of DAC2. See AGY. ARPr 17 O Analog output of DAC3. See AGY. AG Y 13 O Analog output of DAC1. With the proper setting of FSADJ, this output is capable of driving 1.3-V full scale into a 37.5-Ω load. AVDD 11, 14, 18 PWR Analog power supply, nominal 3.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Table 2-1. Terminal Functions (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION SCL 64 B Serial clock line of I2C bus interface. Open-collector. Maximum specified clock speed is 400 kHz (fast I2C). SDA 63 B Serial data line of I2C bus interface. Open-collector. VDD_DLL 4 PWR Power supply of clock doubler, nominal 1.8 V 19, 46, 70 PWR I/O ring power, 1.8 V or 3.3 V nominal VS_IN 44 I/O Vertical source synchronization.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 3.1 www.ti.com Data Manager (DMAN) The data manager is the block that transforms the selected input video data format present on the chip input bus(es) to an internal 10-bit three-channel representation. Supported input formats include 10-/8-bit ITU-R.BT656 with embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit SMPTE274M/296M with embedded sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync.
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THS8200 www.ti.com 3.1.5 SLES032D – JUNE 2002 – REVISED JUNE 2013 Display Timing Generator (DTG) The display timing generator is responsible for the generation of the correct frame format including all sync, equalization and serration pulses. In master timing mode, the DTG is synchronized to external synchronization inputs, either from the dedicated device terminals HS_IN, VS_IN, and FID or is synchronized to the identifiers extracted from the input data stream, as selected by the DMAN mode.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 3.1.10 D/A Converters (DAC) THS8200 contains three DACs operating at up to 205 MSPS and with an internal resolution of 11 bits. Each DAC contains an integrated video sync inserter. The sync(s) is (are) inserted by means of additional current source circuits either on the green/luma (Y) channel only or on all the DAC output channels, to be compliant with both consumer (EIA, sync-on-G/Y) as well as professional (SMPTE, sync-on-all) standards.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 4 Detailed Functional Description 4.1 Data Manager (DMAN) Table 4-1. Supported Input Formats INPUT INTERFACE TIMING CONTROL SYNCHRONIZATION [PRESET] HDTV-SMPTE296M progressive (720P) X (4:4:4) X (4:2:2) X X X [PRESET] HDTV-SMPTE274M progressive (1080P) X (4:4:4) X (4:2:2) X X X [PRESET] HDTV-SMPTE274M progressive (1080I) X (4:4:4) X (4:2:2) X X [GENERIC] HDTV X (4:4:4) X (4:2:2) X X [PRESET] SDTV-ITU.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Furthermore, Table 4-1 shows for which modes presets are defined. When in a preset video mode, the line-type/breakpoint-pairs that define the frame format (see Section 4.7) are preprogrammed. Therefore the user does not need to define the table with line type/breakpoint settings, nor does the field and frame size need to be programmed.
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THS8200 www.ti.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 • www.ti.com of HS_IN (i.e. the first CLKIN rising edge seeing HS active) and a Cb color component assumed present during that clock period on the input bus. When embedded timing is used in this mode, the SAV/EAV structure also unambiguously defines the CbCr sequence, according to ITU-R.BT656 (for 625I and 525I) and SMPTE293M (for 525P).
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 4.3 www.ti.com Clock Generator (CGEN)/Clock Driver (CDRV) The clock generator/clock driver blocks generate all on-chip clocks for 4:2:2 to 4:4:4 and 2x video oversampling. The DMAN setting controls whether the input data is 4:2:2 or 4:4:4 sampled, and whether a 30-, 20- or 10-bit interface is used. This selection affects the clock input frequency assumed to be present on CLKIN. • 30-bit 4:4:4: 1x pixel clock.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 For the offset values, a value of 1/4 of the desired digital offset needs to be programmed in the individual offset register, so a typical offset of 512 (offset over 1/2 of the video range) requires programming a value of 128 decimal into the offset<1,2,3> registers, where again <1,2,3> defines the output channel affected, with similar convention as shown previously.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com SUBADDRESS REGISTER NAME VALUE 0x0E csc_g31 1000 0001 0x0F csc_g32 1101 1100 0x10 csc_b11 0000 0000 0x11 csc_b12 0100 1010 0x12 csc_b21 0000 0010 0x13 csc_b22 0000 1100 0x14 csc_b31 1000 0000 0x15 csc_b32 0011 0000 0x16 csc_offs1 0000 0000 0x17 csc_offs12 0000 1000 0x18 csc_offs23 0000 0010 0x19 csc_offs3 0000 0000 CSC configuration example: HDTV YCbCr to HDTV RGB • Gd = –0.4577*Cr + Yd – 0.
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THS8200 www.ti.com 4.5 SLES032D – JUNE 2002 – REVISED JUNE 2013 Clip/Shift/Multiplier (CSM) There are limits on the code range of the video data if sampled according to ITU or SMPTE standards. In other words, the full 10-bit range [0:1023] is not used to represent video pixels. For example, typically 64 decimal is the lowest code allowed to represent a video signal and corresponds to the blanking level. Similarly for Y, typically the maximum code is 940 decimal.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 4.5.2 www.ti.com Shifting Next the video data can be shifted over a programmable amount downward. The number of codes over which to shift the input video data is set per channel by programming csm_shift_. Shifting of the input video data can be done downwards over 0..255 codes inside the CSM. Ramping Analog Output With Clipping Effect on Top and Bottom 817.3 mV Analog Output From DACs 751.1 mV 700.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Ramping Analog Output With 1:1.1 AC Range Fine Scaling 817.3 mV 770.0 mV Analog Output From DACs 700.0 mV Range After Scaling Up 1:1.1 DC Shifted Original AC Range 0 255 511 767 876 1023 964 Input Digital Codes Figure 4-7. Effect of Scaling the Analog Video Output Figure 4-7 illustrates a shifted analog ramping output. The multiplication factor could be calculated to scale this output range to the full 10-bit range of the DAC.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 1+ d 1 1- d M ag n itu d e -6 dB -40 dB -50 dB 0.20 fs 0.25 fs 0.30 fs 0.37 fs Frequency NOTE: δ = 0.05 dB. fs=74.25 MSPS for 1080I and 720P HDTV formats. Figure 4-8. PB and PR Filter Requirements Based on SMPTE 296M/274M 1+ d 1 1- d M ag n itu d e -12 dB 40 dB 50 dB 0.40 fs 0.50 fs 0.60 fs 0.73 fs Frequency NOTE: δ = 0.05 dB. fs=74.25 MSPS for 1080I and 720P HDTV formats. Figure 4-9.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 1+ d 1 1- d M ag n itu d e -12 dB -40 dB 5.75 6.75 8.0 Frequency (MHz) NOTE: δ = 0.05 dB Figure 4-10. Y and RGB Filter Requirements Based on ITU-R.BT601 1+ d 1 1- d M ag n itu d e -6 dB -40 dB 2.75 3.375 4.0 Frequency (MHz) NOTE: δ = 0.05 dB Figure 4-11. Cb and Cr Filter Requirements Based on ITU-R.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Figure 4-12 through Figure 4-14 illustrate the frequency and phase responses of the interpolating filters. The actual response using the finite-word length coefficients present in THS8200 is shown.
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THS8200 www.ti.com 4.7 4.7.1 SLES032D – JUNE 2002 – REVISED JUNE 2013 Display Timing Generator (DTG) Overview of Functionality THS8200 can generate dedicated Hsync/Vsync/FieldID video synchronization outputs, as well as a composite sync inserted on either the G/Y or all analog output channels. Both types of output synchronization can be available simultaneously and programmed independently.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.2 www.ti.com Functional Description The user should program the DTG with the correct parameters for the current video format. The DTG contains a line and a pixel counter, and a state machine to determine which user−defined line waveform to output for each line on the analog outputs. The pixel counter counts horizontally up to the total number of pixels per line, programmed in 'dtg1_total_pixels'.
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THS8200 www.ti.com • 4.7.2.1 SLES032D – JUNE 2002 – REVISED JUNE 2013 Output synchronization: The available set of output synchronization line types depends on these modes. The user can choose from a number of predefined line types for each mode. In each mode, the user is able to program the timings along the line. However some timings are hard coded by the selected DTG_mode (for example, rise/fall times for sync are different; see DTG Line Type Overview, Section 4.7.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com dtg2_hs_in_dly HS (Input) > RESET Counter = RESET Pixel > Counter = dtg2_hdly > RESET Counter < HS_Out < VS_Out dtg2_vs_in_dly dtg2_hlength VS (Input) > RESET Counter = RESET Line > Counter dtg2_vdly or dtg2_vdly2 = > RESET Counter dtg2_vlength or dtg2_vlength2 Figure 4-15.
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THS8200 www.ti.com 4.7.2.4 SLES032D – JUNE 2002 – REVISED JUNE 2013 Output Synchronization: Hsync/Vsync Outputs These are the HS_OUT and VS_OUT signals, of which the width, position and polarity are programmable in all DTG modes. 4.7.3 DTG Line Type Overview 4.7.3.1 HDTV Mode When an HDTV mode is selected in dtg1_mode (preset or generic), a tri-level sync is inserted on the analog output at the start of every video line.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com f f f Sp/2 V/2 V/2 Sp Sp/2 Sm/2 Sm Sm/2 a c b d e OH Line Sync Timing References 90% 10% f1 f2 f Figure 4-16.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.3.2 www.ti.com Active Video 2 5 1 3 6 4 7 9 8 STATE DURATION 1 Fixed at 2T 2 dtg1_spec_c-4 3 Fixed at 4T 4 dtg1_spec_e dtg1_spec_c-2 5 dtg1_total_pixels dtg1_spec_e dtg1_spec_b 6 dtg1_spec_b dtg1_spec_a-2 7 Fixed at 4T 8 dtg1_spec_a-4 9 Fixed at 2T Figure 4-18. HDTV Line Type ACTIVE_VIDEO 4.7.3.3 FULL NTSP (Full Normal Tri-Level Sync Pulse) Device input data is passed during state #5 if dtg1_pass_through is on.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.3.6 www.ti.
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THS8200 www.ti.com 4.7.3.8 SLES032D – JUNE 2002 – REVISED JUNE 2013 Full BTSP (Full Broad Pulse and Tri-Level Sync Pulse) 2 1 3 8 4 5 6 7 9 11 10 STATE DURATION 1/12 Fixed at 2T 2/13 dtg1_spec_c-4 3/14 Fixed at 4T 4/15 dtg1_spec_d dtg1_spec_c-4 5/16 Fixed at 4T 6/17 dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4 7/18 Fixed at 4T 8/19 dtg1_spec_k dtg1_spec_a-12 9/20 Fixed at 4T 10/21 dtg1_spec_a-4 11/22 Fixed at 2T Figure 4-24.
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Detailed Functional Description Submit Documentation Feedback Product Folder Links: THS8200 Interlace Second Field Interlace First Field Progressive No. 560 No. 1123 No. 1121 No. 561 No. 563 No. 1125 1/2 H No. 562 No. 1124 No. 1125 OV No. 1 No. 1 No. 564 No. 565 Second Field No. 2 First Field No. 2 22 H 45 H No. 566 5H 23 H No. 3 5H No. 3 5H First Field Sync Timing Reference No. 4 No. 4 No. 567 No. 5 No. 5 No. 568 No. 6 No. 6 No. 569 1/2 H No. 7 No. 7 No.
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THS8200 www.ti.com 4.7.3.9 SLES032D – JUNE 2002 – REVISED JUNE 2013 SDTV Mode In SDTV mode, the start of a video line is signaled by the leading edge of a negative-going bi-level sync. f f 90% of Amplitude 50% of Amplitude 10% of Amplitude V f f 90% of Amplitude Sm 50% of Amplitude b a 10% of Amplitude d Figure 4-26.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 1 Line NEQ_NEQ FULL_BSP BSP_BSP FULL_NSP NEQ_BSP BSP_NEQ FULL_NEQ Active Video NSP_ACTIVE Active Video ACTIVE_NEQ Active Video ACTIVE_VIDEO c k c k1 a d d1 h h g i NOTE: All Rise/Fall times are equal to f = 2T Figure 4-27.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.3.10 NEQ_NEQ (Negative Equalization Pulse/Negative Equalization Pulse) 4 9 5 10 3 8 1 6 2 7 STATE DURATION 1 Fixed at 1T 2 dtg1_spec_c 3 Fixed at 2T 4 dtg1_spec_g dtg1_spec_c-4 5 Fixed at 1T 6 Fixed at 1T 7 dtg1_spec_c 8 Fixed at 2T 9 dtg1_spec_g dtg1_spec_c-4 10 Fixed at 1T Figure 4-28. SDTV Line Type NEQ_NEQ 4.7.3.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 4.7.3.12 BSP_BSP (Broad Sync Pulse/Broad Sync Pulse) 4 9 10 5 3 1 8 6 2 7 STATE DURATION 1 Fixed at 1T 2 dtg1_spec_h 3 Fixed at 2T 4 dtg1_spec_g dtg1_spec_h-4 5 Fixed at 1T 6 Fixed at 1T 7 dtg1_spec_h 8 Fixed at 2T 9 dtg1_spec_g dtg1_spec_h-4 10 Fixed at 1T Figure 4-30. SDTV Line Type BSP_BSP 4.7.3.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse) 4 9 10 5 3 8 1 6 7 2 STATE DURATION 1 Fixed at 1T 2 dtg1_spec_c 3 Fixed at 2T 4 dtg1_spec_g dtg1_spec_c-4 5 Fixed at 1T 6 Fixed at 1T 7 dtg1_spec_h 8 Fixed at 2T 9 dtg1_spec_g dtg1_spec_h-4 10 Fixed at 1T Figure 4-32. SDTV Line Type NEQ_BSP 4.7.3.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 4.7.3.16 FULL_NEQ (Full Negative Equalization Pulse) 4 5 6 3 1 2 dtg1_spec_g dtg1_spec_g STATE DURATION 1 Fixed at 1T 2 dtg1_spec_c 3 Fixed at 2T 4 dtg1_spec_g dtg1_spec_c-4 5 dtg1_spec_g 6 Fixed at 1T Figure 4-34. SDTV Line Type FULL_NEQ 4.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video) Video data is always passed during state number 5.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 4.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse) Video data is always passed during state number 5. 5 4 6 11 7 12 3 1 10 8 2 9 STATE DURATION 1 Fixed at 1T 2 dtg1_spec_a 3 Fixed at 2T 4 dtg1_spec_d dtg1_spec_a-3 5 dtg1_spec_g dtg1_spec_d dtg1_spec_k1 6 dtg1_spec_k-1 7 Fixed at 1T 8 Fixed at 1T 9 dtg1_spec_c 10 Fixed at 2T 11 dtg1_spec_g dtg1_spec_c-4 12 Fixed at 1T Figure 4-36.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Example:525I j l Second Field OE1 m n First Field Signal at the Beginning of Each First Field j l First Field OE2 m n Second Field NOTE: l = m = n = 3 j = 20 Figure 4-38.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com The following sections described some of the analog component video output formats that can be generated from THS8200. 4.8.1 RGB Output Without Sync Signal Insertion/General-Purpose Application DAC In this mode, no sync signal is inserted on any of the analog outputs. HS_OUT and VS_OUT signals are generated for output video synchronization. This mode is commonly used in computer graphics video output.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Figure 4-40 shows the linear DAC I/O relationship for either of the two nominal full-scale settings. Ramping Output With Different Full-Scale Ranges Analog Outputs From DACs 1.305 V 0.700 V 0 255 511 767 1023 Input Digital Codes Figure 4-40. Ramping Output With Different Full-Scale Ranges 4.8.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com G Channel Output Waveform E’G 940 Codes to DACs Analog Output 1050 mV 650 mV 350 mV 64 350 mV DC Level Added During Active Video Period Blank Level 50 mV 0 mV Active Video Period Figure 4-41. G-Channel Output Waveform R and B Channel Output Waveform E’RE’B 940 Codes to DACs Analog Output 1050 mV 64 350 mV 350 mV DC Level Added During Active Video Period Blank Level 0 mV Active Video Period Figure 4-42.
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THS8200 www.ti.com 4.8.4 SLES032D – JUNE 2002 – REVISED JUNE 2013 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only In this mode, the output color space is YCrCb. The sync signal is inserted on the Y channel only. Y Channel Output Waveform E’Y 940 Codes to DACs Analog Output 1050 mV 650 mV 64 350 mV 350 mV DC Level Added During Active Video Period Blank Level 50 mV 0 mV Active Video Period Figure 4-44.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Analog Output of Cr and Cb Channels With Sync Insertion 960 896 350 mV 512 50 mV 0 mV Blank Level 128 64 Codes to DACs Analog Output E’cr, E’ cb 700 mV 650 mV Active Video Period Blanking Interval OH Figure 4-46. Analog Output of Cr and Cb Channels With Sync Insertion The ac dynamic range during the active video period is the same on all channels, 700 mV.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Finally, there is a digital output port with data encoded according to ITU-R.BT656. This is a loop-through of the original input bus, prior to any THS8200 internal processing, and thus only provides standard data when input to the THS8200 is provided in a 10-bit ITU-R BT.656 format. This output bus could be used to connect to a separate NTSC/PAL video encoder.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com The I2C interface supports fast I2C, i.e., SCL up to 400 kHz. WRITE FORMAT S Slave address(w) A Sub-address A Data0 A S Start condition Slave address(w) 0100 0000 (0x40) if I2CA = 0, or 0100 0010 (0x42) if I2CA = 1 A Acknowledge, generated by the THS8200 Sub-address Sub-address of the first register to write, length: 1 byte Data0 First byte of the data DataN-1 Nth byte of the data P Stop condition ......
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 5 I2C Registers 5.1 I2C Register Map R/W registers can be written and read. R registers are read-only. Table 5-1.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Table 5-1.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Table 5-1.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Table 5-1.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 Table 5-1.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 5.2 www.ti.com Register Descriptions Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found in the register map. The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d) notation where listed. 5.2.1 System Control (Sub-Addresses 0x02−0x03) ver(7:0): Device version {version 0x02(7..
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 chip_ms: Chip mode select {chip_ctl 0x03(1)} [0] 0 : slave mode. Device synchronizes to incoming video sync signals, either embedded in ITU-R.BT656 interface or received from dedicated timing signals. 1 : master mode. Device requests video data and generates video input timing signals to external (memory) device, according to the programmed frame/field format.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com tst_ydelay(1:0): Y delay path control {tst_cntl2 0x1B(7:6)} [00] Adjusts the delay of the Y channel during YCbCr modes tst_fastramp: DAC test control, fast ramp {tst_cntl2 0x1B(1)} [0] 0 : Normal operation 1 : DAC outputs a ramp at 2x clock rate. tst_slowramp: DAC test control, slow ramp {tst_cntl2 0x1B(0)} [0] 0 : Normal operation 1 : DAC outputs a ramp at 2x clock rate divided by 64,000.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com dtg1_spec_e(8:0): Sync to active video (HDTV)/Color bar start (VESA) {dtg1_spec_deh_msb 0x2B(6) and [0 1100 0000] = [192d] dtg1_spec_e_lsb 0x2A(7:0)} Distance from negative-to-positive transition of tri-level sync to start of active video (HDTV mode).
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 dtg1_mode(3:0): DTG mode selection {dtg1_mode 0x38(3:0)} [0110] Selects the operation mode of the DTG according to the following table.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 5.2.7 www.ti.com Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F) csm_clip_gy_low(7:0): G/Y low clipping value {csm_clip_gy_low 0x41(7:0)} [0100 0000] Sets the value at which low end clipping occurs on G/Y channel, if clipping is enabled. Range is 0−255. csm_clip_bcb_low(7:0): B/Cb low clipping value {csm_clip_bcb_low 0x42(7:0)} [0100 0000] Sets the value at which low end clipping occurs on B/Cb channel, if clipping is enabled. Range is 0−255.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.
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THS8200 www.ti.com dtg2_hlength(9:0): {dtg2_hlength_msb_hdly_msb 0x71(7:6) and dtg2_hlength_lsb 0x70(7:0)} Sets the duration of the HS_OUT output signal SLES032D – JUNE 2002 – REVISED JUNE 2013 HS_OUT duration [00 0110 0000] dtg2_hdly(12:0): HS_OUT delay {dtg2_hlength_msb_hdly_msb 0x71(4:0) and [0 0000 0000 0010] dtg2_hdly_lsb 0x72(7:0)} Sets the pixel value that the HS_OUT signal is asserted on.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com dtg2_ip_fmt: Interlaced/progressive-scan indicator {dtg2_line_cnt_msb 0x7F(7)} Indicates whether current video frame is progressive (0) or interlaced (1) dtg2_line_cnt(10:0): Line count readback {dtg2_lined_cnt_msb 0x7F(2:0) and dtg2_line_cnt_lsb 0x80(7:0)} Reports the number of Hsync input pulses between consecutive dtg_start signals (i.e.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 misc_ppl(15:0): HS high {misc_ppl_msb 0x87(7:0) and misc_ppl_lsb 0x86(7:0)} Reports the number of clock cycles HS was held high misc_lpf(15:0): VS high {misc_lpf_msb 0x89(7:0) and misc_lpf_lsb 0x88(7:0)} Reports the number of HS counts that VS was held high. 5.2.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 5.3.3 www.ti.com 296M Progressive (720P) Breakpoints Line Type 6 FULL_BTSP 26 FULL_NTSP 746 ACTIVE_VIDEO 751 FULL_NTSP frame_size = 01011101110; 750d field_size = 11111111111; not needed 5.3.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com 6 Application Information 6.1 Video vs Computer Graphics Application THS8200 is a highly integrated and flexible universal analog component video/graphics generator that can be used in any application requiring D/A conversion of video/graphics signals.
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THS8200 www.ti.com 6.2 SLES032D – JUNE 2002 – REVISED JUNE 2013 DVI to Analog YPbPr/RGB Application Together with a DVI receiver, this device forms a two-chip solution to convert video or graphics formats sent over a DVI interface to an analog RGB or YPbPr format using embedded composite sync or separate Hsync, Vsync. THS8200 connects gluelessly to a DVI receiver using its data input bus and HS_IN and VS_IN terminals. TI DVI 1.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com GY[9:0] BPb[9:0] G/Y RPr[9:0] MPEG Decoder/ Graphics Processor/ Video Memory B/Pb R/Pr THS8200 CLKIN HS VS_OUT VS SCL D1CLK SDA DO[9:0] To an I2C Master Device Computer Monitor HS_OUT To an NTSC/PAL Encoder Figure 6-4.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 7 Electrical Characteristics 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted) Supply voltage range (1) −0.5 V to 4.5 V AVDD to AVSS, VDD_IO to GND_IO −0.5 V to 2.5 V DVDD to DVSS, VDD_DLL to DVSS −0.5 V to (VDD_IO + 0.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 7.3 www.ti.com Electrical Characteristics over recommended operating conditions with fCLK = 205 MHz, RFS = Rfs(nom) (unless otherwise noted) 7.
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THS8200 www.ti.com 7.5 SLES032D – JUNE 2002 – REVISED JUNE 2013 Digital Inputs, DC Characteristics PARAMETER IIH TEST CONDITIONS MIN TYP High-level input current IIL Low-level input current IIL(CLK) Low-level input current, CLK IIH(CLK) High-level input current, CLK CI Input capacitance VDD_IO = 3.3 V, Digital inputs and CLK at 0 V for IIL, Digital inputs and CLK at 3.6 V for IIH TA = 25°C MAX µA −1 µA 1 µA −1 µA 5 VDD_IO = 1.8 V 1.5 VDD_IO = 3.3 V 1.5 VDD_IO = 1.8 V 0.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 7.6 www.ti.com Analog (DAC) Outputs PARAMETER TEST CONDITIONS DAC resolution MIN TYP 10 (11 bit internal) 10 (11 bit internal) MAX bits +.05/-1.2 +2/-2 Integral nonlinearity Best-fit VDD_IO = 3.3 V, CLK = 500 kHz Video (0.7 + 0.35 V bias) INL Generic (1.25 + 0 V bias) +1/-2.1 +5/-5 DNL Differential nonlinearity VDD_IO = 3.3 V, CLK = 500 kHz Video (0.7 + 0.35 V bias) +0.2/−0.3 +1/−1 Generic (1.25 + 0 V bias) +0.3/-0.
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THS8200 www.ti.com 7.7 SLES032D – JUNE 2002 – REVISED JUNE 2013 Power Requirements 7.7.1 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels f (MHz) POWER (mW), DLL BYPASSED POWER (mW), DLL USED IAVDD (mA) IDVDD (mA) IVDD_IO (mA) IVDD_DLL (mA) 20 329.91 332.88 93.2 10.4 1.1 0.9 30 338.52 351.72 93.2 15 1.2 4 80 382.47 399.63 93.2 38.5 1.7 5.2 160 450.51 93.2 75.2 2.3 200 476.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 7.7.2 www.ti.com Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels f (MHz) POWER (mW), DLL BYPASSED POWER (mW), DLL USED IAVDD (mA) IDVDD (mA) IVDD_IO (mA) IVDD_DLL (mA) 20 328.26 331.23 93.2 10.4 1.1 0.9 30 336.72 349.92 93.2 15 1.2 4 80 379.92 397.08 93.2 38.5 1.7 5.2 160 447.06 93.2 75.2 2.3 200 472.26 93.2 89 2.
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THS8200 www.ti.com 7.7.3 SLES032D – JUNE 2002 – REVISED JUNE 2013 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels f (MHz) POWER (mW), DLL BYPASSED POWER (mW), DLL USED IAVDD (mA) IDVDD (mA) IVDD_IO (mA) IVDD_DLL (mA) 20 556.95 559.92 162 10.4 1.1 0.9 30 565.56 578.76 162 15 1.2 4 80 609.51 626.67 162 38.5 1.7 5.2 160 677.55 162 75.2 2.3 200 703.05 162 89 2.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 7.7.4 www.ti.com Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels f (MHz) POWER (mW), DLL BYPASSED POWER (mW), DLL USED IAVDD (mA) IDVDD (mA) IVDD_IO (mA) IVDD_DLL (mA) 20 555.30 558.27 162 10.4 1.1 0.9 30 563.76 576.96 162 15 1.2 4 80 606.96 624.12 162 38.5 1.7 5.2 160 674.10 162 75.2 2.3 200 699.30 162 89 2.
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THS8200 www.ti.com 7.8 Nonlinearity Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias INL - Integral Nonlinearity - LSB 7.8.1 SLES032D – JUNE 2002 – REVISED JUNE 2013 0.6 V = 700 mV V(BIAS) = 0 V 0.4 0.2 0.0 0 -0.2 -0.4 -0.6 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 832 896 960 1024 Code DNL - Differential Nonlinearity - LSB Figure 7-5. Integral Nonlinearity vs Code 0.3 V = 700 mV V(BIAS) = 0 V 0.2 0.1 0.0 0 -0.1 -0.2 -0.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias INL - Integral Nonlinearity - LSB 7.8.2 www.ti.com 0.8 0.6 0.4 0.2 0.0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 V = 700 mV V(BIAS) = 350 mV 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 832 896 960 1024 Code DNL - Differential Nonlinearity - LSB Figure 7-7. Integral Nonlinearity vs Code 0.3 V = 700 mV V(BIAS) = 350 mV 0.2 0.1 0.0 0 -0.1 -0.
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THS8200 www.ti.com Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias INL - Integral Nonlinearity - LSB 7.8.3 SLES032D – JUNE 2002 – REVISED JUNE 2013 1.0 V = 1.25 V V(BIAS) = 0 V 0.5 0.0 0 -0.5 -1.0 -1.5 -2.0 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 832 896 960 1024 Code DNL - Differential Nonlinearity - LSB Figure 7-9. Integral Nonlinearity vs Code 0.15 0.10 0.05 0.00 0 -0.05 -0.10 -0.15 -0.20 -0.25 V = 1.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 7.9 www.ti.com Analog Output Bandwidth (sinx/x corrected) at fS = 205 MSPS 1 0 -1 -2 Amplitude - dB -3 -4 -5 -6 -7 -8 -9 fS = 205 MSPS -10 0 10 20 30 40 50 60 70 80 90 100 110 f(O) - Output Frequency - MHz Figure 7-11. Amplitude vs Output Frequency VO - Output Voltage - mV 7.10 Output Compliance vs Full-Scale Adjustment Resistor Value 1300 1250 1200 1150 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 RL = 37.
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THS8200 www.ti.com SLES032D – JUNE 2002 – REVISED JUNE 2013 7.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and Horizontal Line Waveform Detail Vertical Blanking, First Field Vertical Blanking, Second Field Active Video Line Figure 7-13.
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THS8200 SLES032D – JUNE 2002 – REVISED JUNE 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision Comments SLES032 Product Preview release SLES032A Production Data release SLES032B Added note 5 to Table 4-1. Added parameters, updated test conditions, and changed notes in Section 7.5. 96 SLES032C Minor editorial changes throughout SLES032D Removed statement that DLL bypass is for test purposes only in Section 4.
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PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) THS8200PFP NRND Package Type Package Pins Package Drawing Qty HTQFP PFP 80 96 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) 0 to 70 THS8200 D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.