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

  

SLLS037C − MARCH 1988 − REVISED JANUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1

to (2

−1) and Generates an Internal 16×

Clock

D Full Double Buffering Eliminates the Need

for Precise Synchronization

D Standard Asynchronous Communication

Bits (Start, Stop, and Parity) Added or

Deleted to or From the Serial Data Stream

D Independent Receiver Clock Input

D Transmit, Receive, Line Status, and Data

Set Interrupts Independently Controlled

D Fully Programmable Serial Interface

Characteristics:

− 5-, 6-, 7-, or 8-Bit Characters

− Even-, Odd-, or No-Parity Bit Generation

and Detection

− 1-, 1 1/2-, or 2-Stop Bit Generation

− Baud Generation (dc to 256 Kbit/s)

D False Start Bit Detection

D Complete Status Reporting Capabilities

D 3-State TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

D Line Break Generation and Detection

D Internal Diagnostic Capabilities:

− Loopback Controls for Communications

Link Fault Isolation

− Break, Parity, Overrun, Framing Error

Simulation

D Fully Prioritized Interrupt System Controls

D Modem Control Functions (CTS, RTS, DSR,

DTR

, RI, and DCD)

D Easily Interfaces to Most Popular

Microprocessors

D Faster Plug-In Replacement for National

Semiconductor NS16C450

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

RCLK

SIN

SOUT

CS0

CS1

CS2

BAUDOUT

XTAL1

XTAL2

DOSTR

DCD

DSR

CTS

OUT1

DTR

RTS

OUT2

INTRPT

ADS

CSOUT

DDIS

DISTR

N PACKAGE

(TOP VIEW)

OUT1

DTR

RTS

OUT2

INTRPT

18 19

RCLK

SIN

SOUT

CS0

CS1

CS2

BAUDOUT

20 21 22 23

FN PACKAGE

(TOP VIEW)

DCD

DSR

CTS

54 321644

DISTR

DDIS

CSOUT

ADS

XTAL1

XTAL2

DOSTR

DISTR

42 41 4043

24 25 26 27 28

NC − No internal connection

NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please

contact your local distributor or TI Sales Office for more information.

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Summary of content (27 pages)

PAGE 1
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 D Programmable Baud Rate Generator Allows N PACKAGE (TOP VIEW) Division of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 16 × Clock D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR VSS D Full Double Buffering Eliminates the Need for Precise Synchronization D Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial
PAGE 2
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 description The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions in a microcomputer system as a serial input/output interface. The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU.
PAGE 3
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 block diagram Internal Data Bus D7 −D0 2−9 Data Bus Buffer Receiver Shift Register Receiver Buffer Register Line Control Register 11 Receiver Timing and Control 10 SIN RCLK Divisor Latch (LS) Baud Generator 17 BAUDOUT Divisor Latch (MS) A0 A1 A2 CS0 CS1 CS2 ADS MR DISTR DISTR DOSTR DOSTR DDIS CSOUT XTAL1 XTAL2 VCC VSS 31 30 29 14 15 16 28 39 25 24 21 20 26 27 18 19 44 22 Transmitter Timing and Control L
PAGE 4
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 Terminal Functions TERMINAL NO.† I/O DESCRIPTION A0 A1 A2 31 30 29 I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description. ADS 28 I Address strobe.
PAGE 5
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 Terminal Functions (continued) TERMINAL NAME NO.† I/O DESCRIPTION OUT1 OUT2 38 35 O Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high.
PAGE 6
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH‡ VOL‡ TEST CONDITIONS HIgh-level output voltage Low-level output voltage MIN IOH = − 1 mA IOL = 1.6 mA TYP† MAX 2.4 IIkg Input leakage current VCC = 5.25 V, VI = 0 to 5.25 V, IOZ High-impedance output current VCC = 5.25 V, VSS = 0, VO = 0 V to 5.
PAGE 7
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 system switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER tw1 tw2 Pulse duration, clock high td3 td10 Delay time, select to CS output Pulse duration, clock low Delay time, RD1↓ or RD2↑ to data valid td11 Delay time, RD1↑ or RD2↓ to floating data tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ † Only applies when ADS is low.
PAGE 8
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature FIGURE TEST CONDITIONS MAX UNIT td20 td21 Delay time, WR MCR to output PARAMETER 6 CL = 100 pF 100 ns Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns td22 Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns PARAMETER MEASUREMENT INFORMATION tw1 RCLK (9 MHz Max)
PAGE 9
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 ADS 10% 10% tsu1 th1 A0 −A2 90% Valid 10% Valid† 10% tsu2 th2 90% 90% Valid CS0, CS1, CS2 10% CSOUT Valid† 10% th3 td3 td3 90% 90% td4† td5† tw6 th4† td6 90% 90% Active DOSTR, DOSTR 10% tsu3 th5 90% 90% Valid Data D0 −D7 † Applicable only when ADS is tied low. Figure 2.
PAGE 10
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 ADS 10% 10% 10% tsu1 th1 A0 −A2 90% Valid 50% 10% Valid† 10% tsu2 th2 90% 90% Valid CS0, CS1, CS2 Valid† 10% 10% th6 td3† td3† 90% CSOUT 90% tw7 td7† td8† th7† td9 90% 90% Active DISTR, DISTR 10% 10% tdis(R) tdis(R) DDIS 10% 10% td11 td10 90% D0 −D7 Valid Data † Applicable only when ADS is tied low. Figure 3.
PAGE 11
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION RCLK 8 CLKs td12 SAMPLE CLOCK SIN Start Data Bits 5 −8 Parity Stop SAMPLE CLOCK td13 90% INTRPT (RDR/LSI) 10% td14 DISTR, DISTR (RD RBR/LSR) 90% Active Figure 4. Receiver Timing Waveforms SOUT Start Data Bits Parity Stop 50% Start 10% td15 INTRPT (THRE) 90% 90% 50% 50% 10% td18 td17 DOSTR (WR THR) td16 90% 90% td17 90% td19 90% DISTR (RD IIR) Figure 5.
PAGE 12
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION DOSTR (WR MCR) 10% 10% td20 td20 90% RTS, DTR OUT 1, OUT 2 CTS, DSR, DCD 90% 10% td21 INTRPT (MODEM) 90% 50% 50% td22 DISTR (RD MSR) 50% td21 90% RI Figure 6.
PAGE 13
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 APPLICATION INFORMATION D7 −D0 SOUT D7−D0 MEMR or I/OR RTS MEMW or I/ON EIA 232-D Drivers and Receivers DOSTR DTR INTR INTRPT RESET DSR MR A0 C P U SIN DISTR DCD A0 A1 A1 A2 A2 B u s CTS TL16C450 (ACE) ADS RI XTAL1 DOSTR L 3.072 MHz DISTR CS H CS2 XTAL2 CS1 BAUDOUT CS0 RCLK Figure 7.
PAGE 14
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 APPLICATION INFORMATION TL16C450 Alternate Xtal Control XTAL1 A16 −A23 A16 −A23 XTAL2 Address Decoder CS0 BAUDOUT CS1 RCLK CS2 CPU ADS DTR 20 RTS 1 ADS OUT1 RSI/ABT MR AD0 − AD7 AD0 −AD15 A0 −A2 D0 −D7 Buffer PHI1 PHI2 PHI1 PHI2 ADS OUT2 RI 5V DCD 8 DSR 6 CTS 5 SOUT 2 SIN 3 RSTO RO DISTR WR DOSTR TCU AD0 −AD15 INTRPT CSOUT DISTR DDIS 7 NC 1 DOSTR GND (VSS) EIA-232-D Connector
PAGE 15
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION Table 1.
PAGE 16
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION accessible registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS Bit No.
PAGE 17
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response to an interrupt generation. By clearing bits 0 − 3, the IER can also disable the interrupt system. The contents of this register are summarized in Table 3 and are described in the following bulleted list.
PAGE 18
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt identification register (IIR) (continued) Table 4.
PAGE 19
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line control register (LCR) (continued) Table 6. Number of Stop Bits Generated 0 Word Length Selected by Bits 1 and 2 Any word length Number of Stop Bits Generated 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 Bit 2 D Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit.
PAGE 20
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line status register (LSR)† (continued) D Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is generated. THRE is set when the contents of the THR are transferred to the transmitted shift register.
PAGE 21
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION modem status register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change information; when a control input from the modem changes state the appropriate bit is set. All four bits are cleared when the CPU reads the MSR.
PAGE 22
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION Table 7. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK 50 2304 75 1536 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 0.69 2.86 Table 8. Baud Rates Using a 3.
PAGE 23
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION VCC Driver External Clock XTAL1 Optional Oscillator Clock to Baud Generator Logic Optional Clock Output XTAL2 VCC XTAL1 C1 RP Crystal RX2 Oscillator Clock to Baud Generator Logic XTAL2 C2 TYPICAL CRYSTAL OSCILLATOR NETWORK CRYSTAL RP 1 MΩ RX2 C1 C2 3.1 MHz 1.5 kΩ 10 −30 pF 40 −60 pF 1.8 MHz 1 MΩ 1.5 kΩ 10 −30 pF 40 −60 pF Figure 10.
PAGE 24
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION receiver buffer register (RBR) The ACE receiver section consists of a receiver shift register and a RBR. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register. The ACE receiver shift register receives serial data from the serial input (SIN) terminal.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.
PAGE 26
MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
PAGE 27
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