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SLLS177H − MARCH 1994 − REVISED JANUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Programmable Auto-RTS and Auto-CTS

D In Auto-CTS Mode, CTS Controls

Transmitter

D In Auto-RTS Mode, RCV FIFO Contents and

Threshold Control RTS

D Serial and Modem Control Outputs Drive a

RJ11 Cable Directly When Equipment Is on

the Same Power Drop

D Capable of Running With All Existing

TL16C450 Software

D After Reset, All Registers Are Identical to

the TL16C450 Register Set

D Up to 16-MHz Clock Rate for up to 1-Mbaud

Operation

D In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise

Synchronization Between the CPU and

Serial Data

D Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1

to (2

−1) and Generates an Internal 16×

Clock

D Standard Asynchronous Communication

Bits (Start, Stop, and Parity) Added to or

Deleted From the Serial Data Stream

D 5-V and 3.3-V Operation

D Independent Receiver Clock Input

D Transmit, Receive, Line Status, and Data

Set Interrupts Independently Controlled

D Fully Programmable Serial Interface

Characteristics:

− 5-, 6-, 7-, or 8-Bit Characters

− Even-, Odd-, or No-Parity Bit Generation

and Detection

− 1-, 1 1/2-, or 2-Stop Bit Generation

− Baud Generation (dc to 1 Mbit/s)

D False-Start Bit Detection

D Complete Status Reporting Capabilities

D 3-State Output TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

D Line Break Generation and Detection

D Internal Diagnostic Capabilities:

− Loopback Controls for Communications

Link Fault Isolation

− Break, Parity, Overrun, and Framing

Error Simulation

D Fully Prioritized Interrupt System Controls

D Modem Control Functions (CTS, RTS, DSR,

DTR

, RI, and DCD)

description

The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous

communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent

to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the

TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead

by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes

including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a

selectable autoflow control feature that can significantly reduce software overload and increase system

efficiency by automatically controlling serial data flow using RTS

output and CTS input signals.

The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral

device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE

status at any time. The ACE includes complete modem control capability and a processor interrupt system that

can be tailored to minimize software management of the communications link.

Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of

dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal

transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates

a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start

bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to

TXRDY

and RXRDY, which provide signaling to a DMA controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (43 pages)

PAGE 1
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 D Programmable Auto-RTS and Auto-CTS D In Auto-CTS Mode, CTS Controls D D D D D D D D Transmitter In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set U
PAGE 2
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1 NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please contact your local distributor or TI Sales Office for more information.
PAGE 3
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 detailed description autoflow control (see Figure 1) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device.
PAGE 4
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 auto-CTS and auto-RTS functional timing Start SOUT Bits 0 −7 Start Stop Bits 0 −7 Stop Start Bits 0 −7 Stop CTS NOTES: A. When CTS is low, the transmitter keeps sending serial data out. B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. C.
PAGE 5
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 functional block diagram Internal Data Bus D(7 −0) Data Bus Buffer 8 S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register Receiver Timing and Control Line Control Register SIN RCLK RTS A0 Divisor Latch (LS) A1 A2 Baud Generator Divisor Latch (MS) CS0 BAUDOUT CS1 ADS MR RD1 RD2 Transmitter Timing and Control Line Status Register CS2 Select an
PAGE 6
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 Terminal Functions TERMINAL NO. N† NO. FN NO. PT I/O DESCRIPTION A0 A1 A2 28 27 26 31 30 29 28 27 26 I Register select. A0 −A2 are used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses and refer to ADS description. ADS 25 28 24 I Address strobe.
PAGE 7
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 Terminal Functions (Continued) TERMINAL NO. N† NO. FN NO. PT I/O DESCRIPTION 34 31 38 35 34 31 O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting respective modem control register (MCR) bits (OUT1 and OUT2).
PAGE 8
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 9
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 standard voltage (5 V nominal) (continued) Junction temperature range, TJ (see Note 6) MIN NOM MAX 0 25 115 °C 16 MHz Oscillator/clock speed UNIT NOTE 6: These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.
PAGE 10
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 system timing requirements over recommended ranges of supply voltage and operating free-air temperature ALT.
PAGE 11
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 8) ALT.
PAGE 12
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION N tw1 tw2 XIN td2 td1 BAUDOUT (1/1) td1 td2 BAUDOUT (1/2) tw3 tw4 BAUDOUT (1/3) BAUDOUT (1/N) (N > 3) 2 XIN Cycles (N −2) XIN Cycles Figure 5.
PAGE 13
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 −A2 50% 50% Valid † Valid 50% tsu2 th2 CS0, CS1, CS2 50% Valid † Valid 50% th3 tw6 td4 th4† td5 WR1, WR2 td6 50% Active 50% tsu3 th5 Valid Data D7 −D0 † Applicable only when ADS is low Figure 6.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 −A2 Valid 50% 50% Valid† 50% tsu2 th2 CS0, CS1, CS2 50% Valid td7† 50% Valid† th6 tw7 50% th7† td8† 50% RD1, RD2 td9 Active 50% tdis(R) DDIS tdis(R) 50% 50% td10 D7 −D0 td11 Valid Data † Applicable only when ADS is low Figure 7.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION RCLK td12 8 CLKs Sample Clock TL16C450 Mode: SIN Start Data Bits 5− 8 Parity Stop Sample Clock INTRPT (data ready) 50% td13 INTRPT (RCV error) 50% td14 50% 50% RD1, RD2 (read RBR) 50% RD1, RD2 (read LSR) 50% Active Active td14 Figure 8.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION SIN Data Bits 5 −8 Stop Sample Clock Trigger Level INTRPT (FCR6, 7 = 0, 0) 50% (FIFO at or above trigger level) 50% (FIFO below trigger level) td13 (see Note A) td14 INTRPT Line Status Interrupt (LSI) 50% 50% td14 RD1 (RD LSR) Active 50% Active RD1 (RD RBR) 50% NOTE A: For a time-out interrupt, td13 = 9 RCLKs. Figure 9.
PAGE 17
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION RD (RD RBR) 50% Active See Note A SIN (first byte) Stop Sample Clock td13 (see Note B) td14 50% 50% RXRDY NOTE A: This is the reading of the last byte in the FIFO. Figure 11.
PAGE 18
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION Start 50% SOUT Data Bits Parity td15 INTRPT (THRE) 50% Start 50% Stop td16 50% 50% 50% 50% td18 td17 td17 WR 50% (WR THR) 50% 50% td19 RD IIR 50% Figure 13. Transmitter Timing Waveforms WR (WR THR) SOUT Byte #1 50% Data Parity Stop Start 50% td21 td20 TXRDY 50% 50% Figure 14.
PAGE 19
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION WR (WR MCR) 50% 50% td22 td22 RTS, DTR, OUT1, OUT2 50% 50% 50% CTS, DSR, DCD td23 INTRPT (modem) 50% 50% 50% td24 td23 RD2 (RD MSR) 50% RI 50% Figure 16. Modem Control Timing Waveforms tsu4 CTS 50% 50% td25 SOUT 50% Midpoint of Stop Bit Figure 17.
PAGE 20
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION Midpoint of Data Bit 0 15th Character SIN 16th Character td29 td28 50% 50% RTS 50% RBRRD Figure 19.
PAGE 21
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 APPLICATION INFORMATION Receiver Disable WR WR1 TL16C550C (ACE) Microcomputer System Data Bus Data Bus 8-Bit Bus Transceiver D7 −D0 DDIS Driver Disable Figure 21.
PAGE 22
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 APPLICATION INFORMATION Alternate Crystal Control TL16C550C XIN A16 −A23 A16 −A23 XOUT BAUDOUT CS0 Address Decoder CPU CS2 ADS ADS RSI/ABT Buffer AD0 −AD15 PHI1 20 RTS 1 OUT2 A0 −A2 D0 −D7 RI PHI2 ADS PHI2 DTR OUT1 MR AD0 −AD7 PHI1 RCLK CS1 RSTO RD RD1 WR WR1 TCU DCD 8 DSR 6 CTS 5 SOUT 2 SIN 3 INTRPT AD0 −AD15 TXRDY RD2 DDIS 7 WR2 RXRDY 1 EIA-
PAGE 23
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION Table 1.
PAGE 24
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION accessible registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS BIT NO.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION FIFO control register (FCR) The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling. D Bit 0: This bit, when set, enables the transmitter and receiver FIFOs.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) When the receiver FIFO and receiver interrupts are enabled: 1. FIFO time-out interrupt occurs if the following conditions exist: a. At least one character is in the FIFO. b.
PAGE 27
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the five types of interrupts (refer to Table 5) and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table 3 and are described in the following bullets.
PAGE 28
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt identification register (IIR) (continued) Table 5.
PAGE 29
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line control register (LCR) (continued) Table 7. Number of Stop Bits Generated BIT 2 WORD LENGTH SELECTED BY BITS 1 AND 2 NUMBER OF STOP BITS GENERATED 0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 D Bit 3: This bit is the parity enable bit.
PAGE 30
SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line status register (LSR) (continued)† D Bit 2‡: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION modem control register (MCR) (continued) D Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs: − The transmitter SOUT is set high. − The receiver SIN is disconnected. − The output of the TSR is looped back into the receiver shift register input.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION modem status register (MSR) (continued) D Bit 3: This bit is the change in data carrier detect (∆ DCD) indicator. ∆ DCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When ∆ DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION programmable baud generator (continued) Table 9. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 2304 75 1536 110 1047 0.026 134.5 857 0.
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SLLS177H − MARCH 1994 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION programmable baud generator (continued) VCC Driver VCC XIN External Clock XIN C1 Crystal RP Optional Driver Optional Clock Output RX2 Oscillator Clock to Baud Generator Logic XOUT Oscillator Clock to Baud Generator Logic XOUT C2 TYPICAL CRYSTAL OSCILLATOR NETWORK CRYSTAL RP 1 MΩ RX2 C1 C2 3.072 MHz 1.5 kΩ 10 −30 pF 40 −60 pF 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 6-Jul-2009 http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials.
PAGE 37
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL16C550CIPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 TL16C550CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TL16C550CPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16C550CIPTR LQFP PT 48 1000 367.0 367.0 38.0 TL16C550CPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TL16C550CPTR LQFP PT 48 1000 367.0 367.0 38.
PAGE 39
MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
PAGE 40
MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.