Datasheet

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TL16C2550

www.ti.com

SLWS161E –JUNE 2005–REVISED NOVEMBER 2012

1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

Check for Samples: TL16C2550

FEATURES

• Programmable Auto-RTS and Auto-CTS – Baud Generation (DC to 1 Mbit/s)

• In Auto-CTS Mode, CTS Controls Transmitter • False-Start Bit Detection

• In Auto-RTS Mode, RCV FIFO Contents, and • Complete Status Reporting Capabilities

Threshold Control RTS

• 3-State Output TTL Drive Capabilities for

• Serial and Modem Control Outputs Drive a Bidirectional Data Bus and Control Bus

RJ11 Cable Directly When Equipment Is on the

• Line Break Generation and Detection Internal

Same Power Drop

Diagnostic Capabilities:

• Capable of Running With All Existing

– Loopback Controls for Communications

TL16C450 Software

Link Fault Isolation

• After Reset, All Registers Are Identical to the

– Break, Parity, Overrun, and Framing Error

TL16C450 Register Set

Simulation

• Up to 24-MHz Clock Rate for up to 1.5-Mbaud

• Fully Prioritized Interrupt System Controls

Operation With VCC = 5 V

• Modem Control Functions (CTS, RTS, DSR,

• Up to 20-MHz Clock Rate for up to 1.25-Mbaud

DTR, RI, and DCD)

Operation With VCC = 3.3 V

• Available in 48-Pin TQFP (PFB) Package, 32-

• Up to 16-MHz Clock Rate for up to 1-Mbaud

Pin QFN (RHB), or 44-Pin PLCC (FN) Package

Operation With VCC = 2.5 V

• Pin Compatible with TL16C752B (48-Pin

• Up to 10-MHz Clock Rate for up to 625-kbaud

Package PFB)

Operation With VCC = 1.8 V

• In the TL16C450 Mode, Hold and Shift APPLICATIONS

Registers Eliminate the Need for Precise

• Point-of-Sale Terminals

Synchronization Between the CPU and Serial

• Gaming Terminals

Data

• Portable Applications

• Programmable Baud Rate Generator Allows

• Router Control

Division of Any Input Reference Clock by 1 to

• Cellular Data

(2 16 -1) and Generates an Internal 16 × Clock

• Factory Automation

• Standard Asynchronous Communication Bits

(Start, Stop, and Parity) Added to or Deleted

DESCRIPTION

From the Serial Data Stream

The TL16C2550 is a dual universal asynchronous

• 5-V, 3.3-V, 2.5-V, and 1.8-V Operation

receiver and transmitter (UART). It incorporates the

• Independent Receiver Clock Input

functionality of two TL16C550D UARTs, each UART

• Transmit, Receive, Line Status, and Data Set

having its own register set and FIFOs. The two

Interrupts Independently Controlled

UARTs share only the data bus interface and clock

source, otherwise they operate independently.

• Fully Programmable Serial Interface

Another name for the uart function is Asynchronous

Characteristics:

Communications Element (ACE), and these terms will

– 5-, 6-, 7-, or 8-Bit Characters

be used interchangeably. The bulk of this document

– Even-, Odd-, or No-Parity Bit Generation

describes the behavior of each ACE, with the

and Detection

understanding that two such devices are incorporated

into the TL16C2550.

– 1-, 1 1/2-, or 2-Stop Bit Generation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 1.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450.
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TL16C2550 www.ti.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 PIN FUNCTIONS (continued) PIN NAME PFB FN RHB D0-D4 D5-D7 44 -48 1 -3 2-6 7-9 27 - 31 32, 1, 2 DSRA, DSRB DTRA, DTRB GND INTA, INTB IOR 39, 20 41, 25 – 34, 35 37, 38 – 17 22 13 30, 29 19 33. 32 24 21. 22 14 IOW 15 20 12 NC 12, 24, 25, 37 – 9 , 17 OPA, OPB RESET RIA, RIB 32, 9 36 41, 21 35, 15 39 43 ,26 – 24 – I/O DESCRIPTION I/O Data bus (bidirectional).
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME PFB RTSA, RTSB RXA, RXB RXRDYA, RXRDYB FN RHB I/O DESCRIPTION 33, 22 36, 27 23, 15 O Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is available.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 DETAILED DESCRIPTION Autoflow Control (see Figure 1) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com Auto-CTS and Auto-RTS Functional Timing Start SOUT Bits 0−7 Start Stop Bits 0−7 Stop Start Bits 0−7 Stop CTS Figure 2. CTS Functional Timing Waveforms SIN Start Byte N Stop Start Byte N+1 Start Stop Byte Stop RTS RD (RD RBR) 1 2 N N+1 Figure 3.
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TL16C2550 www.ti.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com ORDERING INFORMATION TA –40°C to 85°C PACKAGE TQFP - PFB ORDERABLE PART NAME TOP-SIDE MARKING TL16C2550IPFBRQ1 TL2550RQ Reel of 1000 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT (2) VCC Supply voltage range, VI Input voltage range at any input –0.5 V to 7 V VO Output voltage range –0.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 3.3 V ±10% VCC Supply voltage 3 VI Input voltage 0 VIH High-level input voltage VIL Low-level input voltage VO Output voltage IOH IOL 2.5 2.75 V VCC V 0.7VCC V 0.3V V CC 0 VCC V High-level output current (all outputs) 1.8 mA Low-level output current (all outputs) 3.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS MAX UNIT 2.5 V NOMINAL High-level output voltage (2) (3) VOH IOH = –1 mA Low-level output voltage (2) VOL 1.8 V (3) IOL = 2 mA 0.5 V II Input current VCC = 5.5 V, VSS = 0, VI = 0 to 2.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS MAX UNIT 5 V NOMINAL VOH High-level output voltage (2) VOL Low-level output voltage (2) IOL = 4 mA 0.4 V II Input current VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, All other terminals floating 10 µA IOZ High-impedance-state output current VCC = 5.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) LIMITS ALT. SYMBOL PARAMETER FIGURE TEST CONDITIONS 1.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 SPACER TYPICAL CHARACTERISTICS 0.5 VCC = 2.5 V TA = 22°C 1.0 Divisor = 1 0.9 Divisor = 2 0.3 Divisor = 3 Divisor = 10 Divisor = 255 0.2 ICC − Supply Current − mA 0.4 ICC − Supply Current − mA Divisor = 1 1.1 VCC = 1.8 V TA = 22°C 0.1 Divisor = 2 0.8 Divisor = 3 0.7 Divisor = 10 Divisor = 255 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 0.0 10 0 2 4 f − Frequency − MHz 6 G001 12 14 16 Figure 7. 2.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) A2 −A0 50% Valid 50% td5 CSA, CSB th4 50% 50% th3 td4 IOW 50% 50% tw6 tsu3 th5 Valid Data D7 −D0 Figure 11. Write Cycle Timing Waveforms A2 −A0 50% Valid 50% th7 td8 CSA, CSB 50% 50% td7 th6 tw7 IOR 50% 50% td10 D7 −D0 td11 Valid Data Figure 12.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) RCLK (Internal) td12 8 CLKs Sample Clock (Internal) TL16C450 Mode: RXA, RXB Start Data Bits 5−8 Parity Stop Sample Clock INT (data ready) 50% td13 INT (RCV error) 50% td14 50% 50% IOR (read RBR) 50% IOR (read LSR) 50% Active Active td14 Figure 13.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) RXA, RXB Data Bits 5−8 Stop Sample Clock (Internal) Trigger Level INT (FCR6, 7 = 0, 0) 50% 50% (FIFO at or above trigger level) (FIFO below trigger level) td13 (see Note A) INT Line Status Interrupt (LSI) td14 50% 50% td14 IOR (RD LSR) Active 50% IOR (RD RBR) 50% Active Figure 14.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) IOR (RD RBR) 50% Active See Note A RXA, RXB (first byte) Stop Sample Clock (Internal) td13 (see Note B) td14 50% 50% RXRDYA, RXRDYB Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) IOR (RD RBR) Active 50% See Note A RXA, RXB (first byte that reaches the trigger level) Sample Clock (Internal) td13 (see Note B) td14 50% RXRDYA, RXRDYB 50% Figure 17.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Byte 1 IOW (WR THR) 50% Data TXA, TXB Parity Stop Start 50% td21 td20 TXRDYA, TXRDYB 50% 50% Figure 19. Tranceiver Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) Byte 16 IOW (WR THR) 50% Data TXA, TXB Parity td21 td20 TXRDYA, TXRDYB Start 50% Stop 50% 50% FIFO Full Figure 20.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) tsu4 CTSA, CTSB 50% 50% td25 TXA, TXB 50% Midpoint of Stop Bit Figure 22. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms Midpoint of Stop Bit RXA, RXB td26 td27 50% 50% RTSA, RTSB 50% IOR Figure 23. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms Midpoint of Data Bit 0 RXA, RXB 15th Character 16th Character td28 td29 50% 50% RTSA, RTSB 50% IOR Figure 24.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com APPLICATION INFORMATION TXA, B D7 −D0 D7 −D0 MEMR or I/OR MEMW or I/OW INTR C P U B u s RESET A0 A1 A2 RXA, B IOR RTSA, B IOW DTRA, B INTA, B DSRA, B RESET EIA-232-D Drivers and Receivers CDA, B A0 CTSA, B A1 RIA, B A2 TL16C2550 XTAL1 CS CSA, B 3.072 MHz 33 pF XTAL2 (Optional) 33 pF Figure 25.
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TL16C2550 www.ti.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com PRINCIPLES OF OPERATION REGISTER SELECTION Table 1.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 Accessible Registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS DLAB = 0 BIT NO.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com Table 4. Receiver FIFO Trigger Level BIT 7 BIT 6 RECEIVER FIFO TRIGGER LEVEL (BYTES) 0 0 01 0 1 04 1 0 08 1 1 14 FIFO Interrupt Mode Operation When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows: 1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 FIFO Polled Mode Operation With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO polled mode of operation. Because the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user program checks receiver and transmitter status using the LSR.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com Table 5.
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TL16C2550 www.ti.com • • • • • SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked. Bit 4: This bit is the even parity select bit.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 • • www.ti.com at least one byte is written to the transmit FIFO. Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty. Bit 7: In the TL16C450 mode, this bit is always cleared.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 Modem Status Register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com Table 9. Baud Rates Using a 1.8432-MHz Crystal PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL DESIRED BAUD RATE DIVISOR USED TO GENERATE 16× CLOCK 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 0.69 2.86 Table 10. Baud Rates Using a 3.
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TL16C2550 www.ti.com SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 Figure 27. Typical Clock Circuits Table 11. Typical Crystal Oscillator Network Crystal RP RX2 (Optional) C1 C2 3.072 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF 1.8432 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF 16 MHz 1 MΩ 0 kΩ 33 pF 33 pF Receiver Buffer Register (RBR) The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte FIFO.
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TL16C2550 SLWS161E – JUNE 2005 – REVISED NOVEMBER 2012 www.ti.com Table 13. Typical Package Weight 34 PACKAGE WEIGHT IN GRAMS 48-Pin TQFP PFB 0.2 32-Pin TQFP RHB 0.15 44-Pin PLCC FN 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q2 TL16C2550IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 TL16C2550IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TL16C2550PFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16C2550IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TL16C2550IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TL16C2550PFBR TQFP PFB 48 1000 367.0 367.0 38.0 TL16C2550RHBR VQFN RHB 32 3000 338.1 338.1 20.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.