Datasheet
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FEATURES
DESCRIPTION/ORDERING INFORMATION
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
• Programmable Auto- RTS and Auto- CTS • Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
• In Auto- CTS Mode, CTS Controls Transmitter
From the Serial Data Stream
• In Auto- RTS Mode, RCV FIFO Contents and
• 5-V, 3.3-V, and 2.5-V Operation
Threshold Control RTS
• Independent Receiver Clock Input
• Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on the • Transmit, Receive, Line Status, and Data Set
Same Power Drop Interrupts Independently Controlled
• Capable of Running With All Existing • Fully Programmable Serial Interface
TL16C450 Software Characteristics:
• After Reset, All Registers Are Identical to the – 5-, 6-, 7-, or 8-Bit Characters
TL16C450 Register Set
– Even-, Odd-, or No-Parity Bit Generation
• Up to 24-MHz Clock Rate for up to 1.5-Mbaud and Detection
Operation With V
CC
= 5 V
– 1-, 1 ＝ -, or 2-Stop Bit Generation
• Up to 20-MHz Clock Rate for up to 1.25-Mbaud
– Baud Generation (dc to 1 Mbit/s)
Operation With V
CC
= 3.3 V
• False-Start Bit Detection
• Up to 48-MHz Clock Rate for up to 3-Mbaud
• Complete Status Reporting Capabilities
Operation with V
CC
= 3.3 V (ZQS Package Only,
• 3-State Output TTL Drive Capabilities for
Divisor = 1)
Bidirectional Data Bus and Control Bus
• Up to 40-MHz Clock Rate for up to 2.5-Mbaud
• Line Break Generation and Detection
Operation with V
CC
= 3.3 V (ZQS Package Only,
• Internal Diagnostic Capabilities:
Divisor ≥ 2)
– Loopback Controls for Communications
• Up to 16-MHz Clock Rate for up to 1-Mbaud
Link Fault Isolation
Operation With V
CC
= 2.5 V
– Break, Parity, Overrun, and Framing Error
• In the TL16C450 Mode, Hold and Shift
Simulation
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial • Fully Prioritized Interrupt System Controls
Data
• Modem Control Functions ( CTS, RTS, DSR,
• Programmable Baud Rate Generator Allows DTR, RI, and DCD)
Division of Any Input Reference Clock by 1 to
• Available in 48-Pin PT, 48-Pin PFB, 32-Pin
(2
16
– 1) and Generates an Internal 16 × Clock
RHB, and 24-Pin ZQS Packages
The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) of
the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the
TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver
FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software
overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS
input signals.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.