TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 D D D D D D D D IBM PC/AT Compatible Two TL16C550 ACEs Enhanced Bidirectional Printer Port 16-Byte FIFOs Reduce CPU Interrupts Up to 16-MHz Clock Rate for up to 1-Mbaud Operation Transmit, Receive, Line Status, and Data Set Interrupts on Each Channel Independently Controlled Individual Modem Control Signals for Each Channel D D Programmable Serial Interface Characteristics for Each
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 BDO NC NC NC INT1 INT2 SLIN INIT AFD STB GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 INT0 PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC ENIRQ TXR
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 functional block diagram CTS0 DSR0 DCD0 RI0 SIN0 CS0 DB0 – DB7 28 24 31 25 29 26 ACE #1 30 41 45 9 22 32 14 – 21 RTS0 DTR0 SOUT0 INT0 RXRDY0 TXRDY0 8 8 CTS1 DSR1 DCD1 RI1 SIN1 CS1 A0 – A2 IOW IOR RESET CLK 35 – 33 13 12 5 11 8 10 ACE #2 6 62 60 61 3 42 RTS1 DTR1 SOUT1 INT1 RXRDY1 TXRDY1 3 36 Select and Control Logic 37 39 44 BDO 8 4 8 ERR SLCT BUSY PE ACK
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions TERMINAL I/O DESCRIPTION 10 I Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place. ACK generates a printer port interrupt during its positive transition. 56 75 I/O Line printer autofeed.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION 78 O Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK. INT2 is enabled by bit 4 of the write control register. Upon reset, INT2 is in the high-impedance state. Its mode is also controlled by ENIRQ. 37 53 I Input /output read strobe.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION 39, 23 O Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry. A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the transmitter is disabled (RESET is asserted low), the transmitter register is empty, or when in the loop mode.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 recommended operating conditions Supply voltage, VDD MIN NOM MAX UNIT 4.75 5 5.25 V VDD 0.8 V VDD 0.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Note 4 and Figure 4) MIN MAX UNIT tw4 tsu1 Pulse duration, IOR ↓ 80 ns Setup time, CSx valid before IOR ↓ (see Note 5) 15 ns tsu2 th1 Setup time, A2 – A0 valid before IOR ↓ (see Note 5) 15 ns Hold time, A2 – A0 valid after IOR ↑ (see Note 5) 20 ns th2 td1 Hol
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Note 11 and Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, interrupt THRE ↓ to SOUT ↓ at start See Figure 6 8 24 RCLK cycles td6 Delay time, SOUT ↓ at start to interrupt THRE ↑ See Note 12 and Figure 6 8 9 RCLK cycles td7 D
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 parallel port timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 16 and Figures 15, 16, and 17) MIN MAX UNIT tsu7 th6 Setup time, data valid before STB ↓ 1 µs Hold time, data valid after STB ↑ 1 µs tw6 td10 Pulse duration, STB ↓ 1 µs Delay time, BUSY ↑ to ACK ↓ Defined by printer td11 tw7 Delay time, BUSY ↓ to ACK ↓
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION TL16C552A Data Bus Serial Channel 1 Buffers 9-Pin D Connector Serial Channel 2 Buffers 9-Pin D Connector Address Bus Dual ACE and Printer Port Control Bus Option Jumpers Parallel Port R/C Network 25-Pin D Connector Figure 3.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Valid 50% A2, A1, A0 50% th3 CS0, CS1, CS2 Valid 50% 50% tsu4 th4 td3 tsu5 50% Active IOW 50% 50% Active td4 tw5 or IOR Active 50% tsu6 th5 DB0 – DB7 Valid Data Figure 5.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION IOW (WR THR) Byte #16 50% Start of Byte #16 SOUT Data Parity Start Stop tpd5 TXRDY td8 50% FIFO Full 50% Figure 8.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION SIN Start Data Bits 5 – 8 Parity Stop Sample CLK Trigger Interrupt (FCR6, 7 = 0, 0) (FIFO at or above trigger level) 50% 50% td9 (FIFO below trigger level) tpd7 IOR (RD RBR) 50% 50% LSI Interrupt Active 50% tpd7 Active IOR (RD LSR) 50% Figure 10.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION IOR (RD RBR) Active 50% (see Note A) SIN (first byte) Stop Sample CLK RXRDY td9 (see Note B ) tpd8 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. If FCR0 = 1, td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles. Figure 12.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION IOW (WR MCR) 50% 50% tpd9 tpd9 50% RTS, DTR CTS, DSR, DCD 50% 50% 50% tpd10 INT0, INT1, 1 INT, 2 INT tpd10 50% 50% 50% 50% tpd11 IOR (RD MSR) tpd12 50% 50% RI Figure 14. Modem Control Timing Waveforms DATA Valid 50% 50% tsu7 STB th6 50% 50% tw6 50% ACK BUSY ÉÉÉÉÉ ÉÉÉÉÉ 50% td12 50% td10 tw8 td11 50% 50% tw7 Figure 15.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION ENIRQ ACK 50% 50% td14 td13 50% INT2 50% Line Printer Status Register, Bit 2 (PRINT) 50% td(int (see Note A) IOR (RD_LPS) 50% NOTE A: A timing value is not provided for td(int) in the tables because the line printer status register, bit 2 (PRINT) is an internal signal. Figure 16.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic abbreviations for the internal registers are shown in Table 1. Table 1.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION accessible registers Using the CPU, the system programmer has access to and control over any of the ACE registers that are summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION FIFO control register (FCR) This write-only register is at the same location as the interrupt identification register. It enables and clears the FIFOs, sets the trigger level of the receiver FIFO, and selects the type of DMA signaling. D D D D D D Bit 0: FCR0 enables both the transmitter and receiver FIFOs.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. When the following conditions exist, a FIFO character time-out interrupt occurs: a. Minimum of one character in FIFO b. The last received serial character is longer than four previous continuous-character times (if two stop bits are programmed, the second one is included in the time delay). c.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION interrupt enable register (IER) (continued) D D D D Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled. Bit 2: When IER2 is set, the receiver line status interrupt is enabled. Bit 3: When IER3 is set, the modem status interrupt is enabled. Bits 4 – 7: IER4 through IER7 are cleared.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register (LCR) The format of the data character is controlled by the LCR. The LCR can be read. Its contents are described in the following bulleted list and shown in Figure 19. D D D D D D Bits 0 and 1: LCR0 and LCR1 are the word length select bits. The number of bits in each serial character is programmed as shown.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register (LCR) (continued) Line Control Register LCR LCR LCR LCR LCR LCR LCR LCR 7 6 5 4 3 2 1 0 Word Length Select 0 0 1 1 0 = 5 Data Bits 1 = 6 Data Bits 0 = 7 Data Bits 1 = 8 Data Bits Stop Bit Select 0 = 1 Stop Bits 1 = 1.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line printer port (continued) Table 6 summarizes the configuration of the PD port based on the combinations of the logic level on the PEMD terminal and the value of the direction control bit (DIR). Table 6.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION register 2 line printer control register The line printer control (LPC) register is a read/write port that controls the PD0 – PD7 direction and drives the printer control lines. Write operations set or clear these bits, whereas read operations return the state of the last write operation to this register.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register (LSR) The LSR is a single register that provides status indicators. The LSR bits shown in Table 9 are described in the following bulleted list. D D D D D Bit 0: DR is the data ready bit. When set, an incoming character is received and transferred into the receiver buffer register or in the FIFO.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register (LSR) (continued) NOTE: The LSR may be written to. However, this function is intended only for factory test. It should be considered as read only by applications software. Table 9.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION master reset (continued) Table 10. RESET Effects on Registers and Signals REGISTER/SIGNAL RESET CONTROL RESET Interrupt enable register Reset All bits cleared (0 – 3 forced and 4 – 7 permanent) Interrupt identification register Reset Bit 0 is set,, bits 1,, 2,, 3,, 6,, and 7 are cleared,, and bits 4 – 5 are permanentlyy cleared.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem control register (MCR) (continued) D Bits 5 – 7: MCR5 – MCR7 are permanently cleared.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem status register (MSR) (continued) D D D D D Bit 3: MSR3 is the delta data carrier detect (∆ DCD) bit. ∆ DCD indicates that the DCD input to the serial channel has changed states since the last time it was read by the CPU. Bit 4: MSR4 is the clear-to-send (CTS) bit.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION parallel port registers The TL16C552A parallel port can connect the device to a Centronic-style printer interface. When chip select 2 (CS2) is low, the parallel port is selected. Table 12 shows the registers associated with this parallel port.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator (continued) Table 14. Baud Rates Using a 1.8432-MHz Crystal BAUD RATE DESIRED 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 DIVISOR (N) USED TO GENERATE 16x CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 – – 0.026 0.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator (continued) Table 16. Baud Rates Using an 8-MHz Clock BAUD RATE DESIRED 50 75 110 134.
TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 PRINCIPLES OF OPERATION programming The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR. These control words define the character length, number of stop bits, parity, baud rate, and modem interface. While the control registers can be written to in any order, the IER should be written to last because it controls the interrupt enables.
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