Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear-IC

TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Pin-to-Pin Compatible With the Existing

TL16C550B/C

Programmable 16- or 64-Byte FIFOs to

Reduce CPU Interrupts

Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls

Transmitter

In Auto-RTS Mode, Receiver FIFO Contents

and Threshold Control RTS

Serial and Modem Control Outputs Drive a

RJ11 Cable Directly When Equipment Is on

the Same Power Drop

Capable of Running With All Existing

TL16C450 Software

After Reset, All Registers Are Identical to

the TL16C450 Register Set

Up to 16-MHz Clock Rate for Up to 1-Mbaud

Operation

In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise

Synchronization Between the CPU and

Serial Data

Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1

to (2

–1) and Generates an Internal 16 ×

Clock

Standard Asynchronous Communication

Bits (Start, Stop, and Parity) Added or

Deleted to or From the Serial Data Stream

5-V and 3-V Operation

Low-Power Mode

Independent Receiver Clock Input

Independently Controlled Transmit,

Receive, Line Status, and Data Set

Interrupts

Fully Programmable Serial Interface

Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters

– Even-, Odd-, or No-Parity Bit Generation

and Detection

– 1-, 1 1/2-, or 2-Stop Bit Generation

– Baud Generation (DC to 1 Mbits Per

Second)

False Start Bit Detection

Complete Status Reporting Capabilities

3-State Output CMOS Drive Capabilities for

Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities:

– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,

DTR

, RI, and DCD)

Available in 44-Pin PLCC and 64-Pin SQFP

Industrial Temperature Range Available for

64-Pin SQFP

description

The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE),

which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up

(character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO

mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.

The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte

for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode.

In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload

and increase system efficiency by automatically controlling serial data flow through the RTS

output and the CTS

input signals (see Figure 1).

The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and

parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The

ACE includes complete modem control capability and a processor interrupt system that can be tailored to

minimize software management of the communications link.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (35 pages)

PAGE 1
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transmitter In Auto-RTS Mode, Receiver FIFO Contents and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Powe
PAGE 2
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 description (continued) The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (216 – 1) and producing a 16 × reference clock for the internal transmitter logic. Provisions are also included to use this 16 × clock for the receiver logic.
PAGE 3
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 functional block diagram Internal Data Bus 9–2 D(7 – 0) 8 Data Bus Buffer S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register A1 A2 CS0 CS1 CS2 ADS MR RD1 RD2 WR1 WR2 DDIS TXRDY XIN SIN 10 Receiver Timing and Control Line Control Register A0 11 RCLK 36 RTS 31 30 29 Divisor Latch (LS) 14 Divisor Latch (MS) Baud Generator 17 15
PAGE 4
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 Terminal Functions TERMINAL NO. FN NO. PM I/O DESCRIPTION A0 A1 A2 31 30 29 20 18 17 I Register select. A0 – A2 are used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses and ADS signal description. ADS 28 15 I Address strobe.
PAGE 5
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 Terminal Functions (Continued) TERMINAL NO. FN NO. PM I/O DESCRIPTION RD1 RD2 24 25 9 10 I Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register.
PAGE 6
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 autoflow control (continued) ACE1 ACE2 Serial to Parallel RCV FIFO Flow Control SIN SOUT CTS RTS Parallel to Serial XMT FIFO Flow Control D7– D0 D7– D0 Parallel to Serial XMT FIFO Flow Control SOUT SIN RTS CTS Serial to Parallel RCV FIFO Flow Control Figure 1.
PAGE 7
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 enabling auto-RTS and auto-CTS (continued) The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or 56 bytes for 64-byte mode (see Figure 3). SIN Start Byte N Stop Start Byte N+1 Start Stop Byte Stop RTS RD (RD RBR) 1 2 N N+1 NOTES: A. N = receiver FIFO trigger level B.
PAGE 8
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 recommended operating conditions low voltage (3.3 V nominal) MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 V Input voltage, VI 0 VCC V High-level input voltage, VIH (see Note 3) 0.
PAGE 9
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) low voltage (3.3 V nominal) VOH VOL IOZ IIL PARAMETER High-level output voltage† TEST CONDITIONS IOH = – 1.8 mA IOL = 3.
PAGE 10
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 system timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT.
PAGE 11
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 commercial maximum switching characteristics, VCC = 4.75 V, TJ = 115°C PARAMETER tPLH tPHL INTRINSIC DELAY (ns) DELTA DELAY (ns/pF) CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF – 0.92 0.571 7.65 27.66 47.66 56.23 – 0.79 0.312 3.89 14.83 25.76 30.45 Output rise time, XO 10.86 40.42 69.98 82.65 Output fall time, XO 5.47 20.90 36.34 42.
PAGE 12
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER ALT.
PAGE 13
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 – A2 50% 50% Valid † Valid 50% tsu2 th2 CS0, CS1, CS2 50% th3 tw6 td4 td5 WR1, WR2 Valid † Valid 50% th4† td6 50% Active 50% tsu3 th5 Valid Data D7 – D0 † Applicable only when ADS is low Figure 5.
PAGE 14
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 – A2 Valid 50% 50% Valid† 50% tsu2 th2 CS0, CS1, CS2 50% Valid td7† td8† RD1, RD2 50% 50% Valid† th6 tw7 th7† td9 Active 50% tdis(R) DDIS 50% tdis(R) 50% 50% td10 td11 Valid Data D7 – D0 † Applicable only when ADS is low Figure 6.
PAGE 15
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION RCLK td12 8 Clocks Sample Clock TL16C450 Mode: SIN Start Data Bits 5 – 8 Parity Stop Sample Clock INTRPT (data ready) 50% td13 INTRPT (receiver error) 50% td14 50% 50% RD1, RD2 (read RBR) 50% RD1, RD2 (read LSR) 50% Active Active td14 Figure 7.
PAGE 16
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION SIN Data Bits 5 – 8 Stop Sample Clock Trigger Level INTRPT (FCR6, 7 = 0, 0) 50% (FIFO at or above trigger level) 50% (FIFO below trigger level) td13 (see Note A) td14 Line Status INTRPT (LSI) 50% 50% td14 RD1 (RD LSR) Active 50% Active RD1 (RD RBR) 50% NOTE A: For a time-out interrupt, td13 = 9 RCLKs. Figure 8.
PAGE 17
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION RD (RD RBR) 50% Active See Note A SIN (first byte) Stop Sample Clock td13 (see Note B) RXRDY td14 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. For a time-out interrupt, td13 = 9 RCLKs. Figure 10.
PAGE 18
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION Start 50% SOUT Data Bits Parity td15 INTRPT (THRE) Start 50% Stop td16 50% 50% 50% 50% 50% td18 td17 td17 WR THR 50% 50% 50% td19 RD IIR 50% Figure 12. Transmitter Timing Waveforms WR (WR THR) SOUT Byte #1 50% Data Parity Stop Start 50% td21 td20 TXRDY 50% 50% Figure 13.
PAGE 19
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION WR (WR MCR) 50% 50% td22 td22 RTS, DTR, OUT1, OUT2 50% 50% 50% CTS, DSR, DCD td23 INTRPT (modem) 50% 50% 50% td24 td23 RD2 (RD MSR) 50% RI 50% Figure 15. Modem Control Timing Waveforms tsu4 CTS 50% 50% td25 SOUT 50% Midpoint of Stop Bit Figure 16.
PAGE 20
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION SOUT D7 – D0 D7 – D0 MEMR or I/OR MEMW or I/ON INTR C P U B U S RESET A0 RD1 RTS WR1 DTR INTRPT DSR MR DCD A0 A1 A1 A2 SIN EIA 232-D Drivers and Receivers CTS TL16C750 (ACE) RI A2 ADS XIN WR2 L 3.072 MHz RD2 CS H CS2 XOUT CS1 BAUDOUT CS0 RCLK Figure 18.
PAGE 21
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 APPLICATION INFORMATION TL16C750 XIN A16 – A23 A16 – A23 XOUT 18 Alternate Crystal Control 19 17 14 BAUDOUT CS0 Address Decoder CPU 15 16 RCLK CS1 CS2 DTR 28 ADS RTS 36 1 OUT2 35 A0 – A2 AD0 – AD7 D0 – D2 Buffer 43 RI 42 PHI1 20 OUT1 MR AD0 – AD15 37 38 ADS 39 RSI/ABT 10 DCD PHI2 8 41 6 DSR CTS PHI1 ADS PHI2 RSTO RD 24 TCU 20 WR
PAGE 22
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION Table 1.
PAGE 23
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION accessible registers The system programmer, through the CPU, has access to and control over any of the ACE registers. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS Bit No.
PAGE 24
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION FIFO control register (FCR) The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling. D D D D D D D Bit 0: FCR0 when set enables the transmit and receive FIFOs.
PAGE 25
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. FIFO time-out interrupt occurs when the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay). c.
PAGE 26
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table3 and are described in the following bulleted list.
PAGE 27
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION interrupt identification register (IIR) (continued) Table 5.
PAGE 28
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION line control register (LCR) (continued) Table 7. Number of Stop Bits Generated D D D D D BIT 2 WORD LENGTH SELECTED BY BITS 1 AND 2 NUMBER OF STOP BITS GENERATED 0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 Bit 3: This bit is the parity enable bit.
PAGE 29
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION line status register (LSR)† (continued) D D D D D Bit 3‡: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character does not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR.
PAGE 30
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION modem control register (MCR) (continued) D D Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs: – SOUT is asserted high. – SIN is disconnected. – The output of the TSR is looped back into the RSR input.
PAGE 31
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION modem status register (MSR) (continued) D D D D D D Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that RI to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated.
PAGE 32
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION programmable baud generator (continued) Table 9. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 2304 75 1536 110 1047 0.026 134.5 857 0.
PAGE 33
TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION programmable baud generator (continued) VCC VCC Driver XIN XIN External Clock C1 Crystal RP Optional Driver Optional Clock Output RX2 Oscillator Clock to Baud Generator Logic XOUT Oscillator Clock to Baud Generator Logic XOUT C2 TYPICAL CRYSTAL/ OSCILLATOR NETWORK CRYSTAL RP 1 MΩ RX2 C1 C2 3.072 MHz 1.5 kΩ 10 – 30 pF 40 – 60 pF 1.
PAGE 34
PACKAGE OPTION ADDENDUM www.ti.
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.