Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear-IC

45 44

43 42 41 40 39 38 37

TXRDYA

RIA

CDA

DSRA

CTSA

DTRB

RESET

DTRA

RTSA

OPA

RXRDYA

INTA

INTB

CTSB

RTSB

RIB

DSRB

IOR

RXRDYB

GND

CDB

IOW

XTAL2

XTAL1

21 22

15 2019

RXB

RXA

TXRDYB

TXA

TXB

OPB

CSA

CSB

PTPackage

(TopView)

P0028-05

TL16C752B

www.ti.com

SLLS405C –DECEMBER 1999–REVISED JUNE 2010

3.3-V Dual UART With 64-Byte FIFO

Check for Samples: TL16C752B

FEATURES

• Supports 3.3-V Operation

• Pin Compatible With ST16C2550 With • Software Selectable Baud Rate Generator

Additional Enhancements

• Prescaler Provides Additional Divide By 4

• Up to 1.5 Mbps Baud Rate When Using Crystal Function

(24-MHz Input Clock)

• Fast Access Time 2 Clock Cycle IOR/IOW

• Up to 3 Mbps Baud Rate When Using Pulse Width

Oscillator or Clock Source (48-MHz Input

• Programmable Sleep Mode

Clock)

• Programmable Serial Interface Characteristics

• 64-Byte Transmit FIFO

– 5-, 6-, 7-, or 8-Bit Characters

• 64-Byte Receive FIFO With Error Flags

– Even, Odd, or No Parity Bit Generation and

• Programmable and Selectable Transmit and

Detection

Receive FIFO Trigger Levels for DMA and

– 1, 1.5, or 2 Stop Bit Generation

Interrupt Generation

• False Start Bit Detection

• Programmable Receive FIFO Trigger Levels for

• Complete Status Reporting Capabilities in

Software/Hardware Flow Control

Both Normal and Sleep Mode

• Software/Hardware Flow Control

• Line Break Generation and Detection

– Programmable Xon/Xoff Characters

• Internal Test and Loopback Capabilities

– Programmable Auto-RTS and Auto-CTS

• Fully Prioritized Interrupt System Controls

• Optional Data Flow Resume by Xon Any

• Modem Control Functions (CTS, RTS, DSR,

Character

DTR, RI, and CD)

• DMA Signalling Capability for Both Received

and Transmitted Data

NC -No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

PAGE 1
TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 3.3-V Dual UART With 64-Byte FIFO Check for Samples: TL16C752B FEATURES • • • 1 • • • • • • • • • • Pin Compatible With ST16C2550 With Additional Enhancements Up to 1.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TL16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION IOR 19 I Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register defined by address bits A0-A2 onto the TL16C752B data bus (D0-D7) for access by an external CPU. IOW 15 I Write input (active low strobe).
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM Modem Control Signals Control Signals Bus Interface Status Signals Control and Status Block Divisor Control Signals Baud Rate Generator Status Signals UART_CLK RX Receiver FIFO 64-Byte Receiver Block Logic Vote Logic RX TX Transmitter FIFO 64-Byte Transmitter Block Logic TX B0415-01 NOTE: The vote logic determines whether the RX data is a logic 1 or 0.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 TRIGGER LEVELS The TL16C752B provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com auto-CTS The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte. CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Software Flow Control Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3-0]. Table 1 shows software flow control options.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com TX Xoff1/2 characters are transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0]. Xon1/2 characters are transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4]. An important note here is that if, after an xoff character has been sent and software flow control is disabled, the UART will transmit Xon characters automatically to enable normal transmission to proceed.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Software Flow Control Example Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Table 4.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Polled Mode Operation In polled mode (IER[3:0]=0000) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO polled mode operation.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Block DMA Transfers (DMA mode 1) Transmitter: TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7). Figure 8 shows TXRDY and RXRDY in DMA mode 1.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Programmable Baud Rate Generator The TL16C752B UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216–1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 9. The output frequency of the baud rate generator is 16x the baud rate.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Table 5. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK 50 2304 75 1536 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 5600 2 0.69 2.86 Table 6. Baud Rates Using a 3.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 VCC Driver VCC XTAL1 External Clock XTAL1 C1 Crystal RP Optional Clock Output Optional Driver XTAL2 RX2 Oscillator Clock to Baud Generator Logic Oscillator Clock to Baud Generator Logic XTAL2 C2 TYPICAL CRYSTAL OSCILLATOR NETWORK CRYSTAL RP RX2 C1 C2 3.072 MHz 1 MW 1.5 kW 10 - 30 pF 40 - 60 pF 1.8432 MHz 1 MW 1.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE / UNIT Supply voltage range, VCC –0.5 V to 3.6 V Input voltage range, VI –0.5 V to VCC +0.5 V Output voltage range, VO –0.5 V to VCC +0.5 V Operating free-air temperature range, TA –40°C to 85°C Storage temperature range, Tstg –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 TIMING REQUIREMENTS TA = –40°C to 85°C, VCC = 3.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 A0–A2 www.ti.com Valid tsu1 CS (A–B) th4 Active td1 th1 tw1 td2 Active IOR td3 td4 Data D0–D7 T0468-01 Figure 11. General Read Timing A0–A2 Valid tsu1 CS (A–B) th4 Active td5 th2 td6 tw2 Active IOW th3 tsu2 Data D0–D7 T0469-01 Figure 12. General Write Timing td19 IOW IOR tsu3 th5 XTAL1 T0470-01 Figure 13.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 IOW Active td7 RTS (A–B) DTR (A–B) Change of State Change of State CD (A–B) CTS (A–B) DSR (A–B) Change of State td8 td8 INT (A–B) Active Active Active td9 Active IOR Active Active td8 Change of State RI (A–B) T0471-01 Figure 14.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Start Bit Stop Bit Data Bits (5–8) RX (A–B) D0 D1 D2 D3 D4 D5 D6 D7 Next Data Start Bit Parity Bit td15 xData Ready RXRDY (A–B) RXRDY td16 Active IOR T0473-01 Figure 16. Receive Ready Timing in Non-FIFO Mode Start Bit Stop Bit Data Bits (5–8) RX (A–B) D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit First Byte That Reaches the Trigger Level td15 Data Ready RXRDY (A–B) RXRDY td16 Active IOR T0474-01 Figure 17.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Start Bit Stop Bit Data Bits (5–8) D0 D1 D2 D3 D4 D5 D6 D7 TX (A–B) Parity Bit 5 Data Bits 6 Data Bits Next Data Start Bit 7 Data Bits td12 Active Tx Ready INT (A–B) td14 td13 Active Active IOW 16 Baud Rate Clock T0475-01 Figure 18.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Start Bit Stop Bit Data Bits (5–8) TX (A–B) D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit 5 Data Bits 6 Data Bits 7 Data Bits IOW D0–D7 Active td18 Byte 32 td17 TXRDY (A–B) Trigger Lead T0477-01 Figure 20. Transmit Ready Timing in FIFO Mode TIMING ERROR CONDITION Texas Instruments has discovered a timing anomaly in two of its newest products in the UART family, namely the TL16C752 and TL16C752B.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 PRINCIPLES OF OPERATION REGISTER MAP Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The programming combinations for register selection are shown in Table 7. All registers shown in bold are accessed by a combination of address pins and register bits. Table 7.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Table 8 lists and describes the TL16C752 internal registers. Table 8.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Receiver Holding Register (RHR) The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location zero of the FIFO is used to store the characters.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 10 shows line control register bit settings. Table 10. Line Control Register (LCR) Bit Settings BIT NO. 1:0 26 BIT SETTINGS Specifies the word length to be transmitted or received.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Line Status Register (LSR) Table 11 shows line status register bit settings. Table 11. Line Status Register (LSR) Bit Settings BIT NO. BIT SETTINGS 0 0 = No data in the receive FIFO 1 = At least one character in the RX FIFO 1 0 = No overrun error 1 = Overrun error has occurred.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 12 shows modem control register bit settings. Table 12. Modem Control Register (MCR) Bit Settings (1) BIT NO. (1) BIT SETTINGS 0 0 = Force DTR output to inactive (high) 1 = Force DTR output to active (low) In loopback controls MSR[5].
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Interrupt Enable Register (IER) The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in response to interrupt generation. Table 14 shows interrupt enable register bit settings. Table 14. Interrupt Enable Register (IER) Bit Settings BIT SETTINGS (1) BIT NO.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com The interrupt priority list is illustrated in Table 16. Table 16.
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TL16C752B www.ti.com SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 Transmission Control Register (TCR) This 8-bit register is used to store the receive FIFO threshold levels to start/stop transmission during hardware/software flow control. Table 18 shows transmission control register bit settings. Table 18. Transmission Control Register (TCR) Bit Settings BIT SETTINGS (1) BIT NO.
PAGE 32
TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com FIFO Ready Register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 20 shows the FIFO ready register bit settings. The trigger level mentioned below refers to the setting in either FCR (when TLR value is zero), or TLR (when it has a nonzero value). Table 20. FIFO Ready Register BIT SETTINGS (1) BIT NO.
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TL16C752B www.ti.
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TL16C752B SLLS405C – DECEMBER 1999 – REVISED JUNE 2010 www.ti.com THERMAL INFORMATION TL16C752B THERMAL METRIC (1) PT UNITS 48 PINS qJA Junction-to-ambient thermal resistance (2) 66.2 qJCtop Junction-to-case (top) thermal resistance (3) 17.6 qJB Junction-to-board thermal resistance (4) 38.6 (5) yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter (6) 34.9 qJCbot Junction-to-case (bottom) thermal resistance n/A (1) (2) (3) (4) (5) (6) 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TL16C752BPTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16C752BPTR LQFP PT 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.