TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 D Integrated Asynchronous-Communications D D D D D D D D Element Consists of Four Improved TL16C550C ACEs Plus Steering Logic In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data Up to 16-MHz Clock Rate for up to 1-
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 DCDA RIA RXA GND D7 D6 D5 D4 D3 D2 D1 D0 INTN VCC RXD RID DCDD FN PACKAGE (TOP VIEW) 9 10 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DCDB RIB RXB VCC NC A2 A1 A0 XTAL1 XTAL2 RESET RXRDY TXRDY GND RXC RIC DCDC DSRA CTSA
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 DSRD CTSD DTRD GND RTSD INTD CSD TXD IOR TXC CSC INTC RTSC VCC DTRC CTSC PM PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 1 2 3 4 5 6 7 17 8 9 10 11 12 13 14 15 16 DSRC DCDC RIC RXC GND RESET XTAL2 XTAL1 A0 A1 A2 VCC RXB RIB DCDB DSRB DSRA CTSA DTRA VCC R
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 RIB DCDB NC NC DCDC RIC RXC GND TXRDY RXRDY RESET NC XTAL2 XTAL1 NC A0 A1 A2 VCC RXB PN PACKAGE (TOP VIEW) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC DSRC CTSC DTRC VCC RTSC INTC CSC TXC IOR NC TXD CSD INTD RTSD GND DTRD CTSD DSRD NC 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 7
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 functional block diagram (per channel) 5 − 66 D(7 − 0) Data Bus Buffer Internal Data Bus 8 S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register Receiver Timing and Control Line Control Register A0 A1 A2 CSA CSB CSC CSD RESET IOR IOW TXRDY XTAL1 XTAL2 RXRDY INTN 7 RXA 14 34 Divisor Latch (LS) 33 32 Baud Generator Divisor Latch (MS) 16 Line Status Register 20
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 Terminal Functions TERMINAL FN NO. PM NO. PN NO. I/O DESCRIPTION 34 33 32 22, 23, 24 48 47 46 I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register to read or write. CSA, CSB, CSC, CSD 16, 20, 50, 54 7, 11, 38, 42 28, 33, 68, 73 I Chip select.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 Terminal Functions (Continued) TERMINAL PM NO. PN NO. I/O DESCRIPTION RIA, RIB, RIC, RID 19, 30, 50, 63 18, 43, 58, 3 I Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone line. The condition of this signal can be checked by reading bit 6 of the modem-status register. RTSA, RTSB, RTSC, RTSD 5, 13, 36, 44 26, 35, 66, 75 O Request to send.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 recommended operating conditions, standard voltage (5 V-nominal) Supply voltage, VCC Clock high-level input voltage at XTAL1, VIH(CLK) Clock low-level input voltage at XTAL1, VIL(CLK) High-level input voltage, VIH Low-level input voltage, VIL MIN NOM MAX UNIT 4.75 5 5.25 V 2 VCC V −0.5 0.8 V 2 VCC V −0.5 0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 recommended operating conditions, low voltage (3.3-V nominal) MIN NOM Supply voltage, VCC 3 3.3 3.6 V Clock high-level input voltage at XTAL1, VIH(CLK) 2 VCC V −0.5 0.8 V 2 VCC V −0.5 0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 4) MIN MAX UNIT tw4 Pulse duration, IOR low 75 ns tsu1 Setup time, CSx valid before IOR low (see Note 2) 10 ns tsu2 Setup time, A2 −A0 valid before IOR low (see Note 2) 15 ns th1 Hold time, A2 −A0 valid after IOR high (see Note 2) 0 ns th2 Hold time, CSx valid aft
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, INTx↓ to TXx↓ at start See Note 7 8 24 RCLK cycles td6 Delay time, TXx↓ at start to INTx↑ See Note 5 8 8 RCLK cycles td7 Delay time, IOW high or low (WR THR) to INTx↑ See Note 5 16 32 RC
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION tw1 Clock (XTAL1) 2V 2V 2V 0.8 V 0.8 V 0.8 V tw2 fclock = 16 MHz MAX (a) CLOCK INPUT VOLTAGE WAVEFORM RESET tw3 (b) RESET VOLTAGE WAVEFORM Figure 1. Clock Input and RESET Voltage Waveforms 2.54 V Device Under Test 680 Ω TL16C554 82 pF (see Note A) NOTE A: This includes scope and jig capacitance. Figure 2.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION A2, A1, A0 Valid 50% 50% th1 Valid CSx 50% 50% tsu1 th2 td1 tsu2 IOR 50% Active 50% 50% td2 tw4 IOW or 50% ten Active Active tdis D7 −D0 Valid Data Figure 4.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION Start Data (5 −8) 50% TXx Parity td5 INTx Start 50% Stop (1 −2) 50% 50% 50% td6 50% 50% tpd1 td7 IOW 50% (WR THR) tpd1 50% 50% tpd2 IOR (RD IIR) 50% Figure 6. Transmitter Timing Waveforms IOW (WR THR) TXx Byte #1 50% Data Parity Stop 50% Start td8 tpd3 TXRDY 50% FIFO Empty 50% Figure 7.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION TL16C450 Mode: SIN (receiver input data) Start Data Bits (5 −8) Parity Stop Sample Clock td9 INTx (data ready or RCVR ERR) 50% 50% tpd4 Active 50% IOR Figure 9.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION RXx Stop Sample Clock td9 (see Note A) INTx (time-out or trigger level) Interrupt 50% (FIFO at or above trigger level) 50% (FIFO below trigger level) tpd4 INTx Interrupt 50% Top Byte of FIFO td9 tpd4 IOR (RD LSR) Active Active IOR (RD RBR) 50% 50% 50% 50% Active Previous BYTE Read From FIFO NOTE A: This is the reading of the last byte in the FIFO
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION IOR (RD RBR) 50% Active (see Note A) SIN (first byte that reaches the trigger level) Stop Sample Clock td9 (see Note B) 50% RXRDY 50% tpd5 NOTES: A. This is the reading of the last byte in the FIFO. B. If FCR0 = 1, td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK. Figure 13.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 tsu6 CTS 50% 50% tpd10 TXx 50% Midpoint of Stop Bit Figure 15. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms Midpoint of Stop Bit RXx tPD11 tPD12 50% 50% RTSx IOR 50% RD RBR Figure 16. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms Midpoint of Data Bit 0 RXx 15th Character 16th Character tpd14 tpd13 50% 50% RTSx IOR 50% RD RBR Figure 17.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether it is read only, write only, or read writable. Table 1.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION accessible registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION FIFO-control register (FCR) The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of the receiver FIFO, and selects the type of DMA signalling. D Bit 0: FCR0 enables the transmit and receive FIFOs. All bytes in both FIFOs can be cleared by clearing FCR0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) The following receiver FIFO character time-out status occurs when receiver FIFO and the receiver interrupts are enabled. 1. When the following conditions exist, a FIFO character time-out interrupt occurs: a. Minimum of one character in FIFO b. No new serial characters have been received for at least four character times.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION interrupt-enable register (IER) The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C, D) output. All interrupts are disabled by clearing IER0 − IER3 of the IER. Interrupts are enabled by setting the appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION interrupt-identification register (IIR) (continued) D Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending. D Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5. D Bit 3: IIR3 is always cleared in the TL16C450 mode.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION line-control register (LCR) (continued) LINE CONTROL REGISTER LCR 7 LCR LCR 6 5 LCR 4 LCR 3 LCR LCR 2 1 LCR 0 Word-Length Select 0 0 1 1 0 = 5 Data Bits 1 = 6 Data Bits 0 = 7 Data Bits 1 = 8 Data bits Stop-Bit Select 0 = 1 Stop Bit 1 = 1.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION line-status register (LSR) (continued) D Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The BI indicator is cleared when the CPU reads the contents of the LSR.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION modem-control register (MCR) The MCR controls the interface with the modem or data set as described in Figure 19. The MCR can be written and read. Outputs RTS and DTR are directly controlled by their control bits in this register. A high input asserts a low signal (active) at the output terminals.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 modem-control register (MCR) (continued) D Bit 6 − Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION modem-status register (MSR) (continued) D Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR. D Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier detect (DCD) input.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION programmable baud-rate generator (continued) Table 9. Baud Rates Using a 1.8432-MHz Crystal BAUD RATE DESIRED DIVISOR (N) USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 2304 — 75 1536 — 110 1047 0.026 134.5 857 0.058 150 768 — 300 384 — 600 192 — 1200 96 — 1800 64 — 2000 58 0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION programmable baud-rate generator (continued) Table 11. Baud Rates Using an 8-MHz Clock BAUD RATE DESIRED DIVISOR (N) USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 10000 — 75 6667 0.005 110 4545 0.010 134.5 3717 0.013 150 333 0.010 300 1667 0.020 600 883 0.040 1200 417 0.080 1800 277 0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 Table 12. Baud Rates Using an 16-MHz Clock BAUD RATE DESIRED DIVISOR (N) USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 20000 0 75 13334 0.00 110 9090 0.01 134.5 7434 0.01 150 6666 0.01 300 3334 −0.02 600 1666 0.04 1200 834 −0.08 1800 554 0.28 2000 500 0.00 2400 416 0.16 3600 278 −0.08 4800 208 0.16 7200 138 0.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION autoflow control (see Figure 20) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can send data. With auto-RTS, RTS becomes active when the receiver can handle more data and notifies the sending serial device.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION auto-CTS and auto-RTS functional timing Start SOUT Bits 0 −7 Start Stop Bits 0 −7 Stop Start Bits 0 −7 Stop CTS NOTES: A. When CTS is low, the transmitter keeps sending serial data out. B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. C.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION reset After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an idle mode until initialization. A high on RESET causes the following: 1. Initializes the transmitter and receiver internal clock counters. 2. Clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE), which are set.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 PRINCIPLES OF OPERATION scratchpad register The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to be used by the programmer to hold data temporarily. TXRDY operation In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO contains at least one byte.
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 Revision History DATE REV PAGE 02 JUNE 2010 E 7 23 FEB 2010 C 37 25 AUG 2005 B 1 29 JUL 2003 A Changes unknown 01 AUG 2001 * Original version NOTE: SECTION terminal functions table DESCRIPTION Added pin numbers to PN package 48-pin PM package drawing and terminal function descriptions were added for the new TL16C554APM device features Added voltage information to Up to 16−MHZ Clo
TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT SLLS509E − AUGUST 2001 − REVISED JUNE 2010 Revision History DATE REV PAGE 3/2/06 B 21 — Near middle of page, changed — — Changed from Product Preview to Production Data. — Typical Characteristics Added Typical Characteristics. 1 Description Split first paragraph into two and started second paragraph on next column to improve flow.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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