Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTL16CP754CPM

TL16CP754C, TL16C754C

www.ti.com

SLLS644G –DECEMBER 2007– REVISED MAY 2011

QUAD UARTS WITH 64-BYTE FIFO

Check for Samples: TL16CP754C, TL16C754C

FEATURES

• ST16C654/654D Pin Compatible With • Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply

Additional Enhancements

• Characterized for Operation From –40°C to

• Support up to 24-MHz Crystal Input Clock 85°C, Available in Commercial and Industrial

(1.5 Mbps) Temperature Grades

• Support up to 48-MHz Oscillator Input Clock • Software-Selectable Baud-Rate Generator

(3 Mbps) for 5-V Operation

• Prescaler Provides Additional Divide-by-4

• Support up to 32-MHz Oscillator Input Clock Function

(2 Mbps) for 3.3-V Operation

• Programmable Sleep Mode

• Support up to 24-MHz Input Clock (1.5 Mbps)

• Programmable Serial Interface Characteristics

for 2.5-V Operation

– 5-, 6-, 7-, or 8-Bit Characters

• Support up to 16-MHz Input Clock (1 Mbps) for

– Even, Odd, or No Parity Bit Generation and

1.8-V Operation

Detection

• 64-Byte Transmit FIFO

– 1-, 1.5-, or 2-Stop Bit Generation

• 64-Byte Receive FIFO With Error Flags

• False Start Bit Detection

• Programmable and Selectable Transmit and

• Complete Status Reporting Capabilities in

Receive FIFO Trigger Levels for DMA and

Both Normal and Sleep Mode

Interrupt Generation

• Line Break Generation and Detection

• Programmable Receive FIFO Trigger Levels for

• Internal Test and Loopback Capabilities

Software/Hardware Flow Control

• Fully Prioritized Interrupt System Controls

• Software/Hardware Flow Control

• Modem Control Functions (CTS, RTS, DSR,

– Programmable Xon/Xoff Characters

DTR, RI, and CD)

– Programmable Auto-RTS and Auto-CTS

• IrDA Capability

• Optional Data Flow Resume by Xon Any

Character

• RS-485 Mode Support

DESCRIPTION

The '754C is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic

hardware/software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each

UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock

source, otherwise they operate independently. Another name for the UART function is Asynchronous

Communications Element (ACE), and these terms are used interchangeably. The bulk of this document

describes the behavior of each ACE, with the understanding that four such devices are incorporated into the

'754C. The '754C offers enhanced features. It has a transmission control register (TCR) that stores received

FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY

provide the user with error indications, operational status, and modem interface control. System interrupts may

be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on

the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and

transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own

desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity

and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.

The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control

operations, and software flow control and hardware flow control capabilities.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (49 pages)

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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com QUAD UARTS WITH 64-BYTE FIFO Check for Samples: TL16CP754C, TL16C754C FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements Support up to 24-MHz Crystal Input Clock (1.5 Mbps) Support up to 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation Support up to 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation Support up to 24-MHz Input Clock (1.5 Mbps) for 2.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com The '754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the TL16C754CPM device. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION A0 24 I Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register Address Map. A1 23 I Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register Address Map.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION 53–60 I/O Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. 1, 17, 32, 48 I Data set ready (active low). These inputs are associated with individual UART channels A through D.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION TXA, TXB, TXC, TXD 8, 10, 39, 41 O Transmit data. These outputs are associated with individual serial transmit channel data from the '754C. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input. During normal mode, TXn is high when no data is being sent.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM NOTE: RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 A. www.ti.com The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a majority vote to determine the logic level received. The Vote logic operates on all bits received. FUNCTIONAL DESCRIPTION The '754C UART is pin compatible with the TL16C754B and ST16C654 UARTs. It provides more enhanced features. All additional features are provided through a special enhanced feature register.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Hardware Flow Control Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is sufficiently full.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com A. When CTS is low, the transmitter keeps sending serial data out. B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but it does not send the next byte. C. When CTS goes from high to low, the transmitter begins sending data again. Figure 2.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 1.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com UART 1 UART 2 Transmit FIFO Receive FIFO Data Parallel to Serial Serial to Parallel Xoff - Xon - Xoff Serial to Parallel Parallel to Serial Xon-1 Word Xon-1 Word Xon-2 Word Xon-2 Word Xoff-1 Word Xoff-1 Word Xoff-1 Word Compare Programmed Xon- Xoff Characters Xoff-2 Word Figure 4. Software Flow Control Example Software Flow Control Example Assumptions: UART1 is transmitting a large text file to UART2.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 2. Register Reset Functions (1) RESET CONTROL REGISTER RESET STATE Interrupt enable register RESET All bits cleared Interrupt identification register RESET Bit 0 is set. All other bits cleared. FIFO control register RESET All bits cleared Line control register RESET Reset to 00011101 (1D hex). Modem control register RESET Bit 6–0 cleared. Bit 7 reflects the inverse of the CLKSEL pin value.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 4.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 6. FIFO Polled Mode Operation DMA Signaling There are two modes of DMA operation, DMA mode 0 or 1. Bit 3 of the FIFO control register, FCR[3], selects the DMA mode. In DMA mode 0 of FIFO disable mode (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1 multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Programmable Baud Rate Generator The '754C UART contains a programmable baud generator that divides reference clock by a divisor in the range between 1 and (216−1). The output frequency of the baud rate generator is 16× the baud rate. An additional divide-by-4 prescaler is also available and can be selected by the CLKSEL pin or MCR[7], as shown in the following.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 5. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16× CLOCK 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 0.69 2.86 Table 6. Baud Rates Using a 3.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 8 shows the crystal clock circuit reference. Ω Ω Ω Ω Ω A. For crystal with fundamental frequency from 1 MHz to 24 MHz B. For input clock frequency higher then 24 MHz, the crystal is not allowed and the oscillator must be used, because the '754C internal oscillator cell can only support the crystal frequency up to 24 MHz. Figure 8.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT VCC Supply voltage range –0.5 6 V VI Input voltage range –0.5 VCC + 0.5 V VO Output voltage range –0.5 VCC + 0.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS, VCC = 2.5 V ±10% over operating free-air temperature range (unless otherwise noted) PARAMETER VCC Supply voltage VI Input voltage VIH MIN NOM MAX UNIT 2.25 2.5 2.75 V 0 VCC V High-level input voltage 1.8 2.75 V VIL Low-level input voltage –0.3 0.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS, VCC = 1.8 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –0.5 mA VOL Low-level output voltage IOL = 1 mA II Input current VCC = 1.98 V, VI = 0 to 1.98 V, VSS = 0, All other terminals floating High-impedance state output current VCC = 1.98 V, VO = 0 to 1.98 V, VSS = 0, IOZ Supply current UNIT V 0.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS, VCC = 3.3 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH High-level output voltage IOH = –1.8 mA VOL Low-level output voltage IOL = 3.2 mA II Input current VCC = 3.6 V, VI = 0 to 3.6 V, VSS = 0, All other terminals floating High-impedance state output current VCC = 3.6 V, VO = 0 to 3.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS All channels active 3.0 Div = 1 VCC = 2.5 V, TA = 25°C TA = 25°C 5 Div = 10 2.0 1.5 1.0 Supply Current, ICC (mA) 2.5 Supply Current, ICC (mA) 6 Div = 1 VCC = 1.8 V, 0.5 Div = 10 4 3 2 1 0.0 0 0 2 4 6 8 10 12 14 16 0 3 6 Frequency, f (MHz) Figure 9. Supply Current vs Frequency (VCC = 1.8 V) 12 15 18 21 24 Figure 10. Supply Current vs Frequency (VCC = 2.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com TIMING REQUIREMENTS TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted) LIMITS PARAMETER tRES TEST CONDITIONS Reset pulse width 1.8 V 2.5 V 3.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 13. General Write Timing A[2:0] Valid Address Valid Address t6s t6s t6h t6h t7w CS t9d t7w IOR t12d t12h t12d t12h D[7:0] Figure 14.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 15. Modem/Output Timing Start Bit Stop Bit Data Bits (5–8) RX (A−D) D0 D1 D3 D2 D4 D5 5 Data Bits 6 Data Bits 7 Data Bits D6 D7 Parity Bit Next Data Start Bit t20d INT (A−D) Active t21d Active IOR 16-Baud Rate Clock Figure 16.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 17. Receive Ready Timing in None FIFO Mode Figure 18.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com 16-Baud Rate Clock Figure 19. Transmit Timing Start Bit Stop Bit Data Bits (5–8) D0 TX (A–D) D1 D2 D3 D4 D5 D6 D7 Next Data Start Bit Parity Bit IOW Active D0–D7 Byte 1 t28d T27d TXRDY (A–D) TXRDY Active Transmitter Ready Transmitter Not Ready Figure 20.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 21.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com PRINCIPLES OF OPERATION Register Map Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table 9.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 10.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Transmit Holding Register (THR) The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The transmit holding register is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location zero of the FIFO is used to store the byte.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 12. Line Control Register (LCR) Bit Settings BIT NO. 1:0 BIT SETTINGS Specifies the word length to be transmitted or received. 00 – 5 bits 01 – 6 bits 10 − 7 bits 11 – 8 bits 2 Specifies the number of stop bits: 0 – 1 stop bits (Word length = 5, 6, 7, 8) 1 – 1.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors remaining in the FIFO. NOTE Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RHR. Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows modem status register bit settings. Table 15. Modem Status Register (MSR) Bit Settings (1) BIT NO.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows interrupt identification register bit settings. Table 17. Interrupt Identification Register (IIR) Bit Settings BIT NO. 0 3:1 BIT SETTINGS 0 = An interrupt is pending 1 = No interrupt is pending 3-Bit encoded interrupt. See Table 16.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Divisor Latches (DLL, DLH) Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of the division. DLL and DLH can only be written to before sleep mode is enabled (i.e., before IER[4] is set).
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Alternate Function Register (AFR) The alternate function register (AFR) is used to enable some extra functionality beyond the capabilities of the original TL16C754. The first of these is a concurrent write mode, which can be useful in more expediently setting up all four UART channels. The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 bps.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Table 24. LOOP and RCVEN Functionality LOOP MODE RCVEN RCVEN = 1 LOOP mode off, MCR4 = 0, RX, TX active RCVEN = 0 RCVEN = 1 LOOP mode on, MCR4 = 1, RX, TX inactive RCVEN = 0 AFR MODE DESCRIPTION AFR = 10 RS-232 Receive threshold, timeout, and error detection interrupts available. Data stored in receive FIFO. AFR = 14 RS-485 Receive threshold, timeout, and error detection interrupts available.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Loopback Figure 23. RS-485 Application Example 1 RS-485 XCVR TSR TX RS-485 BUS DTR DEN REN Loopback RX RSR 48SEN RCVEN UART Figure 24. RS-485 Application Example 2 IrDA Overview Transmit Shift Register Receive Shift Register Int_Tx Tx To Optoelectronic LED Int_Rx Rx From Optoelectronic Pin Diode IREN RCVEN IrDA Converter Baud Clock Reset Figure 25.
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TL16CP754C, TL16C754C www.ti.com SLLS644G – DECEMBER 2007 – REVISED MAY 2011 protocol. The 115.2 kbps rate is a maximum rate. When both ends of the transfer are set up to a lower but matching speed, the protocol still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843 MHz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 30. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones Figure 31. Recommended Strobing For Decoded Data The '754C can decode positive pulses on Rx. The timing is different, but the variation is invisible to the UART. The decoder, which works from the falling edge, now recognizes a zero on the trailing edge of the pulse rather than on the leading edge.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com Figure 33.
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TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com TL16CP754C Programmer's Guide The base set of registers that are used during high speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL16CP754CIPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 TL16CP754CPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL16CP754CIPMR LQFP PM 64 1000 336.6 336.6 41.3 TL16CP754CPMR LQFP PM 64 1000 336.6 336.6 41.
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MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.