TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 D D D D D D D Maximum Throughput 400 KSPS Built-In Reference and 8× FIFO Differential/Integral Nonlinearity Error: ±0.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 functional block diagram VCC 4V Reference REFP REFM 1514 A0 X A1 X A2 X A3 X Analog MUX 1518 A0 A1 A2 A3 A4 A5 A6 A7 Command Decode FIFO 10 Bit × 8 Low Power 10-BIT SAR ADC S/H Conversion Clock CFR SDI M U X SDO CMR (4 MSBs) SCLK CS FS CSTART PWDN Control Logic EOC/(INT) GND AVAILABLE OPTIONS PACKAGED DEVICES TA – 40°C to 85°C 2 20-TSSOP (PW) TL
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 Terminal Functions TERMINAL NAME A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 CS NO. I/O DESCRIPTION 6 7 8 9 10 11 12 13 I Analog signal inputs. The analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal to 1 kΩ.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 Terminal Functions (Continued) TERMINAL NAME SDO NO. TLC1514 TLC1518 1 1 I/O DESCRIPTION O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output format is MSB (D15) first.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 Charge Redistribution DAC _ Ain Control Logic + ADC Code REFM Figure 1. Simplified Model of the Successive-Approximation System serial interface INPUT DATA FORMAT MSB LSB D15–D12 D11–D0 Command Configuration data field Input data is binary. All trailing blanks can be filled with zeros.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 control and timing start of the cycle: D D When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Input data is shifted in on the rising edge, and output data changes on the falling edge of SCLK. This is typically used for an SPI microcontroller, although it can also be used for a DSP.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 control and timing (continued) configuration Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once configured after first power up, the information is retained in the H/W or S/W power-down state. When the device is being configured, a write CFR cycle is issued by the host processor.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 normal sampling When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short sampling) or 24 SCLKs (long sampling). Long sampling helps the input analog signal sampled to settle to 0.5 LSB accuracy when input source resistance is high.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TLC1514/TLC1518 conversion modes (continued) repeat sweep mode (mode 11) Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT) is generated. Then two things may happen: 1.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 timing diagrams The timing diagrams can be categorized into two major groups: nonconversion and conversion. The nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. The conversion cycles are the four modes shown in Figure 7 through Figure 14.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 read cycle (read FIFO or read CFR) (continued) FIFO read cycle The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read command. The first FIFO content is output immediately before the command is decoded.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 write cycle (write CFR) The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle does not generate an EOC or INT nor does it carry out any conversion.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 conversion cycles DSP/normal sampling 1 2 3 4 5 6 7 10 11 12 15 16 28 1 SCLK CS FS ÎÎÎ ÎÎÎ SDI Command ID15 ID14 ID13 INT ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ID12 ID15 tsample (Long) tconv tsample (Short) SDO ÎÎÎÎÎÎ ÎÎÎÎÎÎ Previous Conversion Result EOC OD9 OD8 OD7 OD6 OD5 OD4 OD3 ÎÎÎÎÎ ÎÎÎÎÎ t conv OD0 Figure
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 conversion cycles (continued) Select/Read Cycle Select/Read Cycle CS tsample CSTART ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FS tconvert † SDI INT EOC SDO Previous Conversion Result Hi-Z Previous Conversion Result Hi-Z Hi-Z † This is one of the single shot commands. Conversion starts on next rising edge of CSTART. Figure 9.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 modes using the FIFO: modes 01, 10, 11 timing (continued) Configure Select Conversion #1 From Channel 2 Conversion #4 From Channel 2 Select CS FS tsample tsample tsample tconvert tconvert tconvert CSTART ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ † SDI § ‡ ‡ ‡ ‡ § INT Hi-Z SDO Hi-Z Read FIFO #1 Top of FIFO #2 #3 #4 Ne
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 modes using the FIFO: modes 01, 10, 11 timing (continued) Mode 10 (sweep mode) requires reconfiguration at the start of each new sweep sequence. Once the FIFO is filled up to the programmed threshold, the host has the option to either read the FIFO or configure for other modes.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 modes using the FIFO: modes 01, 10, 11 timing (continued) Conversion From Channel 0 Conversion From Channel 3 Conversion From Channel 0 Configure Conversion From Channel 3 CS tsample(i) >= MIN (tsample) FS (DSP) CSTART tsample (1) tsample (2) tsample (3) tsample (4) tconvert SDI INT ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 FIFO operation Serial OD 12-BIT×8 FIFO ADC 7 6 FIFO Full 5 4 3 2 1 0 FIFO 1/2 Full FIFO 3/4 Full FIFO 1/4 Full FIFO Threshold Pointer Figure 15. TLC1514/TLC1518 FIFO The device has an 8 layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host after the preprogrammed threshold is reached.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 FIFO operation (continued) power down Writing 8000h to the device puts the device into a software power-down state. For a hardware power down, the dedicated PWDN pin provides another way to power down the device asynchronously. These two power-down modes power down the entire device including the built-in reference to save power.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 recommended operating conditions (continued) MIN Transition time, for FS, SCLK, SDI, tt(CLK) Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active), tsu(CS-SCLK) Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active), th(SCLK-CS) Delay time, delay from CS falling ed
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 4.5 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VCC = 5.5 V, IOH = –20 µA at 30 pF load VOL Low-level output voltage VCC = 5.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 reference specifications (0.1 µF and 10 µF between REFP and REFM pins) PARAMETER TEST CONDITIONS Reference input voltage, REFP VCC = 4.5 V Input impedance VCC = 5 5V 5.5 Input voltage difference, REFP – REFM VCC = 4.5 V VCC = 5.5 V Internal reference voltage,REFP – REFM Internal reference start up time VCC = 5.5 V VCC = 4.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION tt(I/O) 90% 50% 10% CS tt(I/O) VIH VIL twH(CS) td(CSL-FSH) VIH FS VIL tsu(FSH-SCLKF) th(FSH-SCLKF) td(SCLK16F-CSH) twH(SCLK) twL(SCLK) th(SCLK-CS) tsu(CS-SCLK) 1 16 VIH SCLK tc(SCLK) VIL tsu(DI-CLK) ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ SDI td(FSL-DOV) td(CSL-DOV) SDO OD9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ th(DI-CLK) V
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VIH CS VIL td(CSH-CSTARTL) twL(CSTART) VIH CSTART VIL td(CSH-EOCH) tt(I/O) tt(I/O) tconvert VOH EOC VOL td(CSTARTH-EOCL) td(EOCH-INTL) td(CSL-INTH) VOH INT VOL Figure 17.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION tt(I/O) tt(I/O) VIH CS twH(CS) tsu(CS-SCLK) VIL td(SCLK16F-CSH) twL(SCLK) tt(CLK) twH(SCLK) 1 16 VIH SCLK VIL tc(SCLK) tsu(DI-CLK) SDI th(DI-CLK) ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ID15 td(CSL-DOV) SDO Hi-Z ID1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIH VIL td(CLK-DOV) OD9 Hi-Z OD0 VOH VOL td(EOCH-DOZ) td(CLK-EOCL
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs TEMPERATURE INTEGRAL NONLINEARITY vs TEMPERATURE 0.250 VCC = 5 V, Internal Reference = 4 V, Internal OSC, Single Shot, Short Sample, Mode 00 µP mode 0.19 DNL – Differential Nonlinearity – LSB INL – Integral Nonlinearity – LSB 0.20 0.18 0.17 0.16 0.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS POWER DOWN CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 0.5 4 Supply Current – mA 3.8 3.7 0.4 0.3 Power Down – µ A 3.9 VCC = 5.5 V, External Reference = 4 V, SCLK = 20 MHz, Single Shot, Short Sample, Mode 00 µP mode 3.6 3.5 3.4 0.2 0.1 0 –0.1 3.3 –0.2 3.2 –0.3 3.1 –0.4 3 –40 25 TA – Temperature – °C 85 VCC = 5.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs SAMPLES 0.25 VCC = 5 V, External Reference = 4 V, SCLK = 20 MHz, Single Shot, Short Sample, Mode 00 DSP Mode 0.20 0.15 0.10 0.05 –0.00 –0.05 –0.10 –0.15 0 512 1024 Samples DNL – Differential Nonlinearity – LSB Figure 26 DIFFERENTIAL NONLINEARITY vs SAMPLES 0.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs SAMPLES 0.20 VCC = 5 V, Internal Reference = 4 V, SCLK = 20 MHz, Single Shot, Short Sample, Mode 00 DSP Mode 0.15 0.10 0.05 –0.00 –0.05 –0.10 –0.15 –0.2 0 512 1024 Samples DNL – Differential Nonlinearity – LSB Figure 28 DIFFERENTIAL NONLINEARITY vs SAMPLES 0.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM vs FREQUENCY 20 VCC = 5 V, External Reference = 4 V Internal OSC SCLK = 20 MHz, Long Sample Mode 00 µP Mode 0 Magnitude – dB –20 –40 –60 –80 –100 –120 –140 0 25 50 75 100 125 150 f – Frequency – kHz Figure 30 SIGNAL-TO-NOISE vs INPUT FREQUENCY –50 SNR – Signal-to-Noise – dB VCC = 5 V, External Reference =
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 10.0 VCC = 5 V, External Reference = 4 V, InternalOSC, Single Shot, Short Sample, Mode 00 µP Mode ENOB – Effective Number of Bits – BITS SINAD – Signal-to-Noise + Distortion – dB –50 –55 –60 –65 –70 9.5 9.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PRINCIPLES OF OPERATION 1023 1111111111 VFS See Notes A and B 1111111110 1022 1111111101 1021 VFT = VFS – 1/2 LSB 513 1000000001 512 1000000000 VZT =VZS + 1/2 LSB Step Digital Output Code VFS Nom 511 0111111111 VZS 0000000001 1 0000000000 0 0.00488 0.00976 2.4937 2.4986 2.5034 4.9898 2 0.00244 0000000010 4.9874 4.9922 0 4.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PRINCIPLES OF OPERATION simplified analog input analysis Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PRINCIPLES OF OPERATION Driving Source† TLC1514/18 Rs VS VI = Input Voltage at AIN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance (MUX on Resistance) Ci = Input Capacitance VC = Capacitance Charging Voltage ri VI VC Ci † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PRINCIPLES OF OPERATION power down calculations i(AVERAGE) = (fS /fSMAX ) × i(ON) + (1–fS /fSMAX ) × i(OFF) CASE 1: If VDD = 5 V, auto power down, and an external reference is used: + 20 kHz f + 400 kHz SMAX i (ON) +X 4 mA operating current and i (OFF) +X 5 mA auto power-down current f S so i (AVERAGE) + 0.05 4000 mA ) 0.95 5 mA + 0.
TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 PRINCIPLES OF OPERATION difference between modes of conversion (continued) REPEAT: Configure FIFO Depth=4 /CONV Mode 01 Select Channel/ 1st Conv (CS or CSTART) 2nd Conv (CS or CSTART) 3rd Conv (CS or CSTART) 4th Conv (CS or CSTART FIFO READ 1 FIFO READ 2 FIFO READ 3 FIFO READ 4 Select Channel 1st Conv (CS or CSTART) 2nd Conv (CS or CSTART) 3rd Conv (CS or CSTART)
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