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TAS5414A, TAS5424A

www.ti.com

SLOS535C –MAY 2009– REVISED APRIL 2011

FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS

Check for Samples: TAS5414A, TAS5424A

FEATURES

Heat Slug Up for the TAS5414A

• TAS5414A – Single-Ended Input

• TAS5424A – Differential Input

• Four-Channel Digital Power Amplifier

• Four Analog Inputs, Four BTL Power Outputs

• Typical Output Power per Channel at 10%

THD+N

– 28 W/Ch Into 4 Ω at 14.4 Vdc

• 44-Pin PSOP3 (DKD) Power SOP Package With

– 45 W/Ch Into 2 Ω at 14.4 Vdc

Heat Slug Up for the TAS5424A

– 58 W/Ch Into 4 Ω at 21 Vdc

• 64-Pin QFP (PHD) Power Package With Heat

Slug Up for TAS5414A

– 116 W/Ch Into 2 Ω at 21 Vdc PBTL

• Designed for Automotive EMC Requirements

• Channels Can Be Paralleled (PBTL) for 1-Ω

Applications

• Qualified According to AEC-Q100

• THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω

• ISO9000:2002 TS16949 Certified

• Patented Pop- and Click-Reduction

• –40°C to 105°C Ambient Temperature Range

Technology

APPLICATIONS

– Soft Muting With Gain Ramp Control

– Common-Mode Ramping

• High-Power OEM/Retail Head Units and

Amplifier Modules Where Feature Densities

• Patented AM Interference Avoidance

and System Configurations Require Reduction

• Patented Cycle-by-Cycle Current Limit

in Heat From the Audio Power Amplifier

• 75-dB PSRR

• Four-Address I

C Serial Interface for Device

DESCRIPTION

Configuration and Control

The TAS5414A and TAS5424A are four-channel

• Channel Gains: 12-dB, 20-dB, 26-dB, 32-dB

digital audio amplifiers designed for use in automotive

head units and external amplifier modules. The

• Load Diagnostic Functions:

TAS5414A and TAS5424A provide four channels at

– Output Open and Shorted Load

23 W continuously into 4 Ω at less than 1% THD+N

– Output-to-Power and -to-Ground Shorts

from a 14.4-V supply. Each channel can also deliver

38 W into 2 Ω at 1% THD+N. The TAS5414A uses

– Patented Tweeter Detection

single-ended analog inputs, while the TAS5424A

• Protection and Monitoring Functions:

employs differential inputs for increased immunity to

– Short-Circuit Protection

common-mode system noise. The digital PWM

topology of the TAS5414A and TAS5424A provides

– Load-Dump Protection to 50 V

dramatic improvements in efficiency over traditional

– Fortuitous Open Ground and Power

linear amplifier solutions. This reduces the power

Tolerant

dissipated by the amplifier by a factor of ten under

– Patented Output DC Level Detection While

typical music playback conditions. The TAS5414A

Music Playing

and TAS5424A incorporate all the functionality

needed to perform in the demanding OEM

– Overtemperature Protection

applications area. They have built-in load diagnostic

– Over- and Undervoltage Conditions

functions for detecting and diagnosing misconnected

– Clip Detection

outputs to help to reduce test time during the

manufacturing process.

• 36-Pin PSOP3 (DKD) Power SOP Package With

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (54 pages)

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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS Check for Samples: TAS5414A, TAS5424A FEATURES Heat Slug Up for the TAS5414A 1 • • • • • • • • • • • • • • • • TAS5414A – Single-Ended Input TAS5424A – Differential Input Four-Channel Digital Power Amplifier Four Analog Inputs, Four BTL Power Outputs Typical Output Power per Channel at 10% THD+N – 28 W/Ch Into 4 Ω at 14.4 Vdc – 45 W/Ch Into 2 Ω at 14.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TAS5414A FUNCTIONAL BLOCK DIAGRAM 3.3 V–5 V TAS5414A, 36 Pins Pullup Resistors System mP AVDD (6.5 V) SDA SCL STANDBY Supplies and References D_BYP A_BYP DVDD (3.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com TAS5424A FUNCTIONAL BLOCK DIAGRAM 3.3 V–5 V TAS5424A, 44 Pins Pullup Resistors System mP AVDD (6.5 V) SDA SCL STANDBY Supplies and References D_BYP A_BYP DVDD (3.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com PIN ASSIGNMENTS AND FUNCTIONS The pin assignments for the TAS5414A and TAS5424A are shown as follows.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 1. TERMINAL FUNCTIONS TERMINAL DKD Package NAME PHD Package TYPE (1) DESCRIPTION TAS5414A NO. TAS5424A NO. TAS5414A NO. A_BYP 13 14 11 PBY Bypass pin for the AVDD analog regulator CLIP_OT W 9 10 6 DO Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It also reports tweeter detection during tweeter mode.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) PVDD DC supply voltage range Relative to GND PVDDMAX Pulsed supply voltage range t ≤ 100 ms exposure PVDDRAMP VALUE UNIT –0.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS(1) (continued) MIN VAIN_5414 (2) VAIN_5424 (2) Analog audio input signal level (TAS5414A) Analog audio input signal level (TAS5424A) fAUDIO_TW Audio frequency for tweeter detect TA Ambient temperature AC-coupled input voltage AC-coupled input voltage MAX UNIT 0 0.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 Filter, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VA_BYP_UV_SET A_BYP UV voltage 4.8 V VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 5.3 V D_BYP pin voltage 3.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT ns tr Rise time for both SDA and SCL signals 1000 tf Fall time for both SDA and SCL signals 300 tw(H) SCL pulse duration, high tw(L) ns 4 μs SCL pulse duration, low 4.7 μs tsu2 Setup time for START condition 4.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS THD+N vs POWER at 1kHz THD+N vs FREQUENCY at 1 Watt 10 10 21 VDC, 4 Ω 14.4 VDC, 4 Ω 1 0.1 THD+N − Total Harmonic Distrotion + Noise − % THD+N − Total Harmonic Distrotion + Noise − % 100 14.4 VDC, 2 Ω 21 VDC, 2 Ω, PBTL 0.01 0.1 1 10 14.4 VDC, 4 Ω 0.01 21 VDC, 4 Ω 100 1k 10k 20k f − Frequency − Hz G001 G002 Figure 3. Figure 4.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) IMD SMPTE 19 kHz, 20 kHz 1:1 NOISE FFT −60 −70 −20 −80 −40 Voltage − dBV IMD SMPTE 19 kHz, 20 kHz 1:1 − dBV 0 −60 −90 −80 −100 −100 −110 −120 10 100 1k 10k −120 10 30k 100 f − Frequency − Hz 1k 10k 30k f − Frequency − Hz G005 G006 Figure 7. Figure 8.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DC DETECT VOLTAGE vs REGISTER 0E VALUES 20 18 DC Detect Voltage − V 16 14 PVDD = 20 V PVDD = 14.4 V 12 10 8 PVDD = 8 V 6 4 2 0 65 6a 6f 74 79 7e 83 88 8d 92 97 9c a1 Register 0E − Hex a6 ab b0 b5 ba bf c4 c9 G009 Figure 11. DC DETECT VOLTAGE vs REGISTER 0F VALUES 0 −2 DC Detect Voltage − V −4 PVDD = 8 V −6 −8 PVDD = 14.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com DESCRIPTION OF OPERATION OVERVIEW The TAS5414A and TAS5424A are single-chip, four-channel, analog-input audio amplifiers for use in the automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments, but with changes needed by the automotive industry. This technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Power FETs The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSon of 75 mΩ for high efficiency and maximum power transfer to the load. These FETs are designed to handle large voltage transients during load dump. Load Diagnostics The TAS5414A and TAS5424A incorporate load diagnostic circuitry designed to help pinpoint the nature of output misconnections during installation.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Short Detection Range Short Detected Open Detection Range Normal Load Detected Open Detected RLoad (Including Wires) 1.5 0.5 1 (Typ) 300 1300 800 (Typ) M0067-01 Figure 14. Open and Shorted Load Detection 2. Tweeter Detection— Tweeter detection is an alternate operating mode that is used to determine the proper connection of a frequency dependent load (such as a speaker with a crossover).
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the affected channel(s) are recorded in the I2C fault register. If the supply or ground short is strong enough to exceed the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents excess current from damaging the output FETs, and operation returns to normal after the short is removed. 3.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 PVDD www.ti.com 50 V 100 ms Max 50 V Max Ramp Rate 15 V/ms Load Dump Protection 29 V–50 V 2 I C Stop Standby Mode POR 2 I C Start 29 V Overvoltage Protection Region 23 V–29 V 26 V 23 V 22 V Hi-Z All Ch’s 14.4 V Normal Operating Region 8 V–22 V Ready to Get Off Hi-Z State Time T0189-01 Figure 15.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 SDA R/ A W 7-Bit Slave Address 7 5 6 4 3 2 www.ti.com 1 8-Bit Register Address (N) 7 0 5 6 4 3 2 1 8-Bit Register Data For Address (N) A 0 7 6 5 4 3 2 1 8-Bit Register Data For Address (N) A 7 0 6 5 4 3 2 1 A 0 SCL Start Stop T0035-01 Figure 16. Typical I2C Sequence Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Random Read As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is a 0.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 3.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 6.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 10.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 14.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 18. External Control Register 6 (0x0D) Output Control D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Low-low state disabled all channels FUNCTION – – – – – – – 1 Set channel 1 to low-low state – – – – – – 1 – Set channel 2 to low-low state – – – – – 1 – – Set channel 3 to low-low state – – – – 1 – – – Set channel 4 to low-low state X X X X – – – – Reserved Table 19.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com EMI Considerations Automotive level EMI performance depends on both careful integrated circuit design and good system level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the TAS5414A and TAS5424A design. The TAS5414A and TAS5424A have minimal parasitic inductances due to the short leads on the PSOP3 package.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Table 24.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com 50 V Load Dump Protection 29 V–50 V LD Reset 26 V OV Protection Region 23 V–29 V OV Reset 23 V PVDD Fault Does Not Reset Until Fault Register 1 Is Read FAULT 2 IC CLK Ready to Get Out of Hi-Z State 15-V OUTx_P or OUTx_M (Filtered) Time t0 t1 Oscillator Start-Up Time Outputs Pulled Down t2 t3 OV Deglitch Time T0191-01 Figure 22.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 tGAIN www.ti.com tCM tCM tGAIN HIZ_Report_x (All Channels) LOW_LOW_Report_x (All Channels) MUTE_Report_x (All Channels) PLAY_Report_x MUTE Pin OUTx_P (Filtered) (All Channels) OUTx_M (Filtered) (All Channels) T0192-02 Figure 23.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com tGAIN tCM tCM tGAIN HIZ_Report_1 HIZ_Report_2,3,4 LOW_LOW_Report_1 LOW_LOW_ Report_2,3,4 MUTE_Report MUTE Pin OUT1_P (Filtered) Pop Pop OUT2,3,4_P (Filtered) T0193-02 Figure 24.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Latched Fault Shutdown and Restart Sequence Control tI2C_CL tDEGLITCH tCM tDEGLITCH PVDD UV Detect tGAIN PVDD Normal Operating Region UV Reset VUV + VUV_HY PVDD UV Hysteresis Region VUV VPOR HIZ_x 2 Internal I C Write MUTE_Report UV_DET Cleared by 2 UV_LATCH External I C Read to Fault Register 1 2 External I C Read FAULT Pin MUTE Pin OUTx_P (Filtered) Pop T0194-02 Figure 25.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com tI2C_CL tDEGLITCH tCM tDEGLITCH PVDD VUV + VUV_HY UV Detect tGAIN PVDD Normal Operating Region UV Reset PVDD UV Hysteresis Region VUV VPOR 2 HIZ_Report_1 Internal I C Write HIZ_Report_2,3,4 MUTE_Report UV_DET Cleared by 2 UV_LATCH External I C Read to Fault Register 1 2 External I C Read FAULT Pin MUTE Pin OUT1_P (Filtered) OUT2,3,4_P (Filtered) Pop Pop Pop T0195-02 Figure 26.
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System Microprocessor Optional 9 6 RLV RRV VSSA2 10 FRV 13 FLV 16 VREFDA FAST MUTE 4.
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Copyright © 2009–2011, Texas Instruments Incorporated Heat Slug System Microprocessor FAST MUTE Optional 330nF 12 11 10 9 8 7 6 5 4 3 2 1 17 PVDD PVDD IN4_P 1uF 22 IN4_M 1uF PVDD 21 1uF 20 IN3_M OUT4_M GND GND OUT3_P OUT3_M GND CPC_ BOT CP CPC_ TOP OUT2_P OUT2_M GND GND OUT1_P OUT1_M OUT4_P 19 IN2_M IN2_P IN1_M IN1_P A_ BYP REXT GND GND CLIP_OTW D_ BYP STANDBY GND MUTE FAULT SCL PVDD PVDD PVDD IN3_P 1uF 1uF 18 1uF 1uF 16 1uF 15 100nF14 I2C_
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com Parallel Operation (PBTL) The TAS5414A and TAS5424A can be used to drive four 4-Ω loads, two 2-Ω loads, or even one 1-Ω load by paralleling BTL channels on the load side of the LC output filter. For parallel operation, identical I2C settings are required for any two paralleled channels (especially gain and current-limit settings) in order to have reliable system performance and evenly dissipated power on multiple channels.
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com • • Thermal grease thermal resistance Heat sink thermal resistance The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W (4.52°C-mm2/W).
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TAS5414A, TAS5424A SLOS535C – MAY 2009 – REVISED APRIL 2011 www.ti.com REVISION HISTORY Changes from Revision A (February 2008) to Revision B Page • Changed all instances of SGND and PGND to GND on all pinout diagrams ....................................................................... 4 • Deleted TAS5424A from PHD package in the Terminal Functions table ............................................................................. 6 • Changed all PGND and SGND pins to GND .......................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5414ATDKDRMQ1 HSSOP DKD 36 500 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.0 Q1 TAS5414ATDKDRQ1 HSSOP DKD 36 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1 TAS5424ATDKDRMQ1 HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5414ATDKDRMQ1 HSSOP DKD 36 500 367.0 367.0 45.0 TAS5414ATDKDRQ1 HSSOP DKD 36 500 367.0 367.0 45.0 TAS5424ATDKDRMQ1 HSSOP DKD 44 500 367.0 367.0 45.0 TAS5424ATDKDRQ1 HSSOP DKD 44 500 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.