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TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12-Bit-Resolution A/D Converter

10-µs Conversion Time Over Operating

Temperature

11 Analog Input Channels

3 Built-In Self-Test Modes

Inherent Sample-and-Hold Function

Linearity Error . . . ±1 LSB Max

On-Chip System Clock

End-of-Conversion Output

Unipolar or Bipolar Output Operation

(Signed Binary With Respect to 1/2 the

Applied Voltage Reference)

Programmable MSB or LSB First

Programmable Power Down

Programmable Output Data Length

CMOS Technology

Application Report Available

†

description

The TLC2543C and TLC2543I are 12-bit, switched-

capacitor, successive-approximation, analog-to-

digital converters. Each device, with three control

inputs [chip select (CS

), the input-output clock, and

the address input (DATA INPUT)], is designed for

communication with the serial port of a host processor

or peripheral through a serial 3-state output. The

device allows high-speed data transfers from the

host.

In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel

multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The

sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high

to indicate that conversion is complete. The converter incorporated in the device features differential

high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry

from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating

temperature range.

The TLC2543C is characterized for operation from T

A

= 0°C to 70°C. The TLC2543I is characterized for

operation from T

A

= –40°C to 85°C. The TLC2543M is characterized for operation from T

A

= –55°C to 125°C.

Copyright  2001, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)

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AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

GND

V

CC

EOC

I/O CLOCK

DATA INPUT

DATA OUT

CS

REF+

REF–

AIN10

AIN9

(TOP VIEW)

DB, DW, J, OR N PACKAGE

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910111213

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I/O CLOCK

DATA INPUT

DATA OUT

CS

AIN3

AIN4

AIN5

AIN6

AIN7

FN PACKAGE

(TOP VIEW)

AIN1

AIN0

AIN10

REF –

AIN2

EOC

AIN8

GND

AIN9

V

CC

REF+

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (34 pages)

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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 D D D D D DB, DW, J, OR N PACKAGE (TOP VIEW) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF – AIN10 AIN9 FN PACKAGE (TOP VIEW) AIN2 AIN1 AIN0 VCC EOC D D D D D D D 12-Bit-Resolution A/D Converter 10-µs Conversion Time Over Op
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 AVAILABLE OPTIONS PACKAGE SMALL OUTLINE TA (DB)† (DW)† PLASTIC CHIP CARRIER CERAMIC DIP PLASTIC DIP (FN)† (J) (N) 0°C to 70°C TLC2543CDB TLC2543CDW TLC2543CFN — TLC2543CN – 40°C to 85°C TLC2543IDB TLC2543IDW TLC2543IFN — TLC2543IN – 55°C to 125°C — — — TLC2543MJ — † Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 Terminal Functions TERMINAL I/O DESCRIPTION 1 – 9, 11, 12 I Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input voltage into a capacitance of 60 pF. CS 15 I Chip select.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TLC2543C, TLC2543I MIN TYP† MAX VOH High level output voltage High-level VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOH = –1.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Linearity error (see Note 5) See Figure 2 ±1 LSB Differential linearity error See Figure 2 ±1 LSB EO Offset error (see Note 6) See Note 2 and Figure 2 ± 1.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 15 V 50 Ω C1 10 µF C2 0.1 µF C3 470 pF 10 Ω _ U1 + VI C1 10 µF TLC2543 AIN0 – AIN10 C3 470 pF C2 0.1 µF 50 Ω – 15 V LOCATION DESCRIPTION U1 C1 C2 C3 OP27 10-µF 35-V tantalum capacitor 0.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 2V CS 0.8 V tsu(CS) I/O CLOCK th(CS) Last Clock 0.8 V 0.8 V NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. Figure 5. CS and I/O CLOCK Voltage Waveforms tt(I/O) tt(I/O) 2V 2V I/O CLOCK 0.8 V 0.8 V 0.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 8 11 12 Sample Cycle B ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 1 Hi-Z State DATA OUT A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 Previous Conversion Data ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ MSB DATA INPUT 7 B7 B6 B5 B4 MSB B3 B2 B1 B11 ÎÎÎÎ ÎÎÎÎ LSB C7 B0 LS
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION CS (see Note A) 1 I/O CLOCK 2 3 4 5 Access Cycle B A7 DATA OUT A6 A5 7 ÎÎÎÎÎÎ ÎÎÎÎÎÎ 8 Sample Cycle B A4 A3 A2 A1 Previous Conversion Data Hi-Z A0 1 B7 ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ MSB DATA INPUT 6 B7 B6 B5 B4 MSB B3 LSB B2 B1 B0 C7 LSB EOC Shift in New Mult
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 8 15 16 Sample Cycle B ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 1 Hi-Z State DATA OUT A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Previous Conversion Data MSB B15 ÎÎÎ ÎÎ LSB DATA INPUT B7 B6 B5 B3 B4 MSB B2 B1 B0 C7
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION power up and initialization After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION data input The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION data output length The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current I/O cycle, allows device start-up without losing I/O synchronization.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION data register, LSB first D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION data format and pad bits (continued) When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT on the rising edge of EOC.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION analog input, test, and power-down mode The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type to reduce input-to-input noise rejection resulting from channel switching.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 PRINCIPLES OF OPERATION converter and analog input The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1).
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 APPLICATION INFORMATION 4095 111111111111 VFS See Notes A and B 4094 111111111110 VFSnom 4093 VFT = VFS – 1/2 LSB 2049 100000000001 2048 100000000000 VZT = VZS + 1/2 LSB Step Digital Output Code 111111111101 2047 011111111111 VZS 000000000001 1 000000000000 0 0.0012 0.0024 2.4564 2.4576 4.9128 2.4588 4.9134 2 0.
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TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to VS within 1/2 LSB can be derived as follows: ǒ Ǔ The capacitance charging voltage is given by V C + VS 1–e–tcńRtCi Where: (1) Rt = Rs + ri The final voltage to 1/2 LSB is given by
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC2543CDBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 TLC2543CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLC2543IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2543CDBR SSOP DB 20 2000 367.0 367.0 38.0 TLC2543CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC2543IDBR SSOP DB 20 2000 367.0 367.0 38.0 TLC2543IDWR SOIC DW 20 2000 367.0 367.0 45.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.