Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 24

SCLK

SDI

EOC/INT

SDO

DGND

CSTART

AGND

COMP

REFM

REFP

AGND

TLC3578, TLC2578

DW OR PW PACKAGE

(TOP VIEW)

SCLK

SDI

EOC/INT

SDO

DGND

CSTART

AGND

COMP

REFM

REFP

AGND

TLC3574, TLC2574

DW, N, OR PW PACKAGE

(TOP VIEW)

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      

    ± 

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

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D 14-Bit Resolution for TLC3574/78, 12-Bit for

TLC2574/2578

D Maximum Throughput 200-KSPS

D Multiple Analog Inputs:

− 8 Single-Ended Channels for

TLC3578/2578

− 4 Single-Ended Channels for

TLC3574/2574

D Analog Input Range: ±10 V

D Pseudodifferential Analog Inputs

D SPI/DSP-Compatible Serial Interfaces With

SCLK up to 25-MHz

D Built-In Conversion Clock and 8x FIFO

D Single 5-V Analog Supply; 3-/5-V Digital

Supply

D Low-Power

− 5.8 mA in Normal Operation

− 20 µA in Power Down

D Programmable Autochannel Sweep and

Repeat

D Hardware-Controlled, Programmable

Sampling Period

D Hardware Default Configuration

D INL: TLC3574/78: ±1 LSB;

TLC2574/78: ±0.5 LSB

D DNL: TLC3574/78: ±0.5 LSB;

TLC2574/78: ±0.5 LSB

D SINAD: TLC3574/78: 79 dB;

TLC2574/78: 72 dB

D THD: TLC3574/78: −82 dB;

TLC2574/78: −82 dB

description

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS

analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate

from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital

input [chip select (CS

), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state

serial data output (SDO). CS

(works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI,

SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being

transferred. When multiple converters connect to one serial port of a DSP, CS

works as the chip select to allow

the host DSP to access the individual converter. CS

can be tied to ground if only one converter is used. FS must

be tied to DV

if it is not used (such as in an SPI interface). When SDI is tied to DV

, the device is set in

hardware default mode after power on and no software configuration is required. In the simplest case, only three

wires (SDO, SCLK, and CS

or FS) are needed to interface with the host.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (49 pages)

PAGE 1
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 D 14-Bit Resolution for TLC3574/78, 12-Bit for D D D D D D D D D D D D D D D TLC2574/2578 Maximum Throughput 200-KSPS Multiple Analog Inputs: − 8 Single-Ended Channels for TLC3578/2578 − 4 Single-Ended Channels for TLC3574/2574 Analog Input Range: ±10 V Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces Wi
PAGE 2
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 description (continued) In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages.
PAGE 3
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 equivalent input circuit VDD REFP Bipolar Signal Scaling MUX 3.94 kΩ Digital Input 1.5 kΩ 9.9 kΩ Ain Ron C(sample)= 30 pF 6.6 kΩ Equivalent Digital Input Circuit REFM Diode Turn on Voltage: 35 V Equivalent Analog Input Circuit Terminal Functions TERMINAL NO.
PAGE 4
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 Terminal Functions (Continued) TERMINAL NO. I/O NAME TLC3574 TLC2574 TLC3578 TLC2578 EOC(INT) 4 4 O DESCRIPTION End of conversion (EOC) or interrupt to host processor (INT) EOC: used in conversion mode 00 only.
PAGE 5
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to AVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, singleended input, normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise noted) TLC3574/78 and TLC2574
PAGE 7
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 AC/DC performance over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise noted) TLC3574/78 DW and PW package device AC/
PAGE 8
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TLC3574/78 DW and PW package device AC/DC performance (continued) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT AC Accuracy—Normal Short Sampling SINAD Signal-to-noise ratio + distortion fi = 20 kHz fi = 100 kHz 79 THD Total harmonic distortion fi = 20 kHz fi = 100 kHz −82 SNR Signal-to-noise ratio fi = 20 kHz f
PAGE 9
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TLC3574I N package device AC/DC performance PARAMETER TEST CONDITIONS TYP† MAX UNIT −1.5 ±1 1.5 LSB −1 ±0.8 1.5 LSB MIN DC Accuracy—Normal Long Sampling EL ED Integral linearity error See Note 3 EO EFS(+) Bipolar zero error See Note 4 −0.30 ±0.08 0.
PAGE 10
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TLC3574I N package device AC/DC performance (continued) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT AC Accuracy—Normal Short Sampling SINAD Signal-to-noise ratio + distortion fi = 20 kHz fi = 100 kHz 76 THD Total harmonic distortion fi = 20 kHz fi = 100 kHz −81 SNR Signal-to-noise ratio fi = 20 kHz fi = 100 kH
PAGE 11
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TLC2574/78 DW and PW package devices AC/DC performance MIN TYP† MAX UNIT See Note 6 −1 ±0.5 1 LSB PARAMETER TEST CONDITIONS DC Accuracy EL ED Integral linearity error −1 ±0.5 1 LSB EO EFS(+) Bipolar zero error See Note 7 −0.30 ±0.08 0.36 %FS Positive full scale error See Note 7 −0.55 ±0.04 0.
PAGE 12
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TLC2574I N package device AC/DC performance MIN TYP† MAX UNIT see Note 6 −1 ±0.7 1 LSB PARAMETER TEST CONDITIONS DC Accuracy EL ED Integral linearity error −1 ±0.7 1 LSB EO EFS(+) Bipolar zero error see Note 7 −0.30 ±0.08 0.36 %FS Positive full-scale error see Note 7 −0.55 ±0.04 0.
PAGE 13
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) SCLK, SDI, SDO, EOC and INT PARAMETERS tc(1) Cycle time of SCLK, 25 pF load (see Note 10) tw(1) Pulse width of SCLK High, at 25-pF load MIN DVDD = 2.
PAGE 14
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CS trigger PARAMETERS MIN TYP MAX UNIT tsu(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load 12 ns td(4) Delay
PAGE 15
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) FS trigger PARAMETERS MIN td(8) tsu(3) Delay time, delay from CS falling edge to FS rising edge at 25-pF load tw(3) Pulse width of FS hig
PAGE 16
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CSTART trigger PARAMETERS MIN td(12) Delay time, delay from CSTART rising edge to EOC falling edge, at 10-pF load tw(4) Pulse width of C
PAGE 17
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 circuit description converter The converters include a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows a simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling period.
PAGE 18
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 analog input mode (continued) When pseudodifferential mode is selected, only two analog input channel pairs are available for the TLC3574 and TLC2574 and four channel pairs for the TLC3578 and TLC2578, because half the inputs are used as the negative input.
PAGE 19
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 circuit description (continued) data format INPUT DATA FORMAT (BINARY) MSB LSB ID[15:12] ID[11:0] Command Configuration data field or filled with zeros OUTPUT DATA FORMAT (READ CONVERSION/FIFO) TLC3574 and TLC3578 TLC2574 and TLC2578 MSB LSB MSB LSB OD[15:2] OD[1:0] OD[15:4] OD[3:0] Conversion result Don’t Car
PAGE 20
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 start of operation cycle (continued) CS initiates the operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation. When CS is high, SDO is in high-impedance state, the signals on SDI are ignored, and SCLK is disabled to clock the serial data.
PAGE 21
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 command period (continued) Table 1.
PAGE 22
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 detailed description (continued) Table 2. Configuration Register (CFR) Bit Definition SDI BIT DEFINITION D11 Always 1. Otherwise the performance is degraded. D10 Conversion output code format select: 0: BOB (bipolar offset binary); D9 1: BTC (binary 2s complement) Sample period select for normal sampling.
PAGE 23
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 sampling period (continued) Normal Long Sampling Mode: It is the same as normal short sampling, except that it lasts 44 SCLKs periods to complete the sampling. Extended Sampling Mode: The external signal, CSTART, triggers sampling and conversion. SCLK is not used for sampling.
PAGE 24
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 conversion mode (continued) SWEEP Mode (Mode 10): During each operation, all of the channels listed in the SWEEP SEQUENCE (D[4:3] of CFR register) are sampled and converted one time according to the programmed sequence. The results are stored in the FIFO.
PAGE 25
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 operation cycle timing CS Initiates Operation 12 SCLKs for Short 44 SCLKs for Long 4 SCLKs t(setup)† SDI § SDO 18 OSC for Internal OSC‡ 72 SCLK for External Clock 15 ns t(convert) t(overhead) t(sample) 4-bit Command 12-bit CFR Data (Optional) 14-bit Data (Previous Conversion) 2-bit Don’t Care Active CS (FS Is Tied
PAGE 26
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 operation cycle timing (continued) After the operation finished, the host has several choices. Table 3 summarizes of operation options. Table 3. Operation Options CONVERSION IS INITIATED BY MODE CS FS CSTART 00 1. Issue new Select/Read operation to read data and start new conversion. 2. Reconfigure the device. 1.
PAGE 27
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 operation timing diagrams (continued) 1 2 3 4 5 6 7 12 13 14 15 16 1 CS ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ FS = High SDI ID15 1D14 ID13 1D12 ID11 ID10 ID9 ID4 ID3 ID2 ID1 ID0 INT OR ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ EOC SDO ÌÌÌ ÌÌÌ ID15 ID14 ÌÌÌÌÌ Hi-Z The dotted lines means signal may or may not exist.
PAGE 28
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 conversion operation 48 SCLKs for Long Sampling 16 SCLKs for Short Sampling 1 CS 2 ÌÌÌ ÌÌ ÌÌÌ ÌÌ FS in High SDI INT 3 4 Select Channel ID15 ID14 ID13 5 6 13 12 7 14 15 1 16 ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌ 1D12 ID15 t(SAMPLE) EOC t(conv) Previous Conversion Result
PAGE 29
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 conversion operation (continued) Select Channel 16 SCLK Select Channel 16 SCLK t(sample) CS Tied to Low CSTART Possible Signal FS t(convert) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ** *** SDI ** INT EOC OR SDO ÌÌ ÌÌ ** Data Lost Previous Conversion Result Hi-Z Conversion Result Hi-Z Hi-Z Possible Signal Select Channe
PAGE 30
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH3 Conversion From CH0 Conversion From CH3 CS ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌ ÌÌ FS SDI ** *** ** ** ** * * * ** * ** ** ** * INT Hi-Z SDO CH0 1st Sweep CH1 ** * CH0 CH3
PAGE 31
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH2 Conversion From CH0 Conversion From CH2 CS FS CSTART ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ Ì Ì Ì *** ** SDI INT 1st SWEEP SDO * * * * CH0 CH0 CH2 CH2 ** * REPEAT CH0 1st FIFO Read Don’t Care *** ** * 2nd FIFO Read READ FIF
PAGE 32
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 FIFO operation Serial SOD ×8 FIFO ADC 7 6 FIFO Full 5 4 3 2 1 0 FIFO 1/2 Full FIFO 3/4 Full FIFO 1/4 Full FIFO Threshold Pointer Figure 20. FIFO Structure FIFO operation (continued) The device has an 8-level FIFO that can be programmed for different thresholds.
PAGE 33
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 2 Reference = 4 V AVDD = 5 V, TA = 25°C 1.5 1 0.5 0 −0.
PAGE 34
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TYPICAL CHARACTERISTICS BIPOLAR ZERO ERROR, POSITIVE FULL SCALE ERROR AND NEGATIVE FULL SCALE ERROR (% FS) vs FREE-AIR TEMPERATURE INL (LSB) AND DNL (LSB) vs FREE-AIR TEMPERATURE 0.500 1.3 Reference = 4 V AVDD = 5 V E0 , E FS(+) and E FS(−) (%FS) INL (LSB) and DNL (LSB) Reference = 4 V AVDD = 5 V INL 1 0.7 0.
PAGE 35
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TYPICAL CHARACTERISTICS SINAD vs INPUT SIGNAL FREQUENCY ENOB vs INPUT SIGNAL FREQUENCY 82 80 13.2 Reference = 4 V AVDD = 5 V TA = 25°C Reference = 4 V AVDD = 5 V TA = 25°C ENOB − (Bits) SINAD − dB 12.8 78 76 12 74 72 1k 12.4 60 k 80 k 20 k 40 k fI − Input Signal Frequency − Hz 11.
PAGE 36
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT AT AUTOPOWER DOWN vs FREE-AIR TEMPERATURE 5.6 4 Reference = 4 V AVDD = 5 V SCLK Stops ICC − Supply Current − µ A I CC − Supply Current − mA Reference = 4 V AVDD = 5 V 5.4 5.2 5 −40.
PAGE 37
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 APPLICATION INFORMATION interface with host Figure 32 shows the examples of the interface between a single converter and host DSP (TMS320C54x DSP) or microprocessor.
PAGE 38
± SLAS262C − OCTOBER 2000 − REVISED MAY 2003 APPLICATION INFORMATION REFP Bipolar Signal Scaling MUX Req 3.94 kΩ Ain 1.5 kΩ Max 9.9 kΩ Converter Ron Vs 6.6 kΩ C(sample) = 30 pF Max C(sample) = 30 pF Req = Thevenin Equivalent Resistance Vs = Thevenin Equivalent Voltage REFM Figure 33. Equivalent Input Circuit Including the Driving Source 38 WWW.TI.
PAGE 39
PACKAGE OPTION ADDENDUM www.ti.
PAGE 40
PACKAGE OPTION ADDENDUM www.ti.com 6-Oct-2008 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PAGE 41
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC2578IPWR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TLC3574IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLC3578IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
PAGE 42
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2578IPWR TSSOP PW 24 2000 367.0 367.0 38.0 TLC3574IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC3578IPWR TSSOP PW 24 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.