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ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Scrambler (zero drift) SOIC 8

  

   

 

SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Extremely Low Offset Voltage ...1 µV Max

D Extremely Low Change on Offset Voltage

With Temperature . . . 0.003 µV/°C Typ

D Low Input Offset Current

500 pA Max at T

= − 55°C to 125°C

D A

. . . 135 dB Min

D CMRR . . . 120 dB Min

D k

SVR

...110 dB Min

D Single-Supply Operation

D Common-Mode Input Voltage Range

Includes the Negative Rail

D No Noise Degradation With External

Capacitors Connected to V

DD−

description

The TLC2652 and TLC2652A are high-precision

chopper-stabilized operational amplifiers using

Texas Instruments Advanced LinCMOS pro-

cess. This process, in conjunction with unique

chopper-stabilization circuitry, produces opera-

tional amplifiers whose performance matches or

exceeds that of similar devices available today.

Chopper-stabilization techniques make possible

extremely high dc precision by continuously

nulling input offset voltage even during variations

in temperature, time, common-mode voltage, and

power supply voltage. In addition, low-frequency

noise voltage is significantly reduced. This high

precision, coupled with the extremely high input

impedance of the CMOS input stage, makes the

TLC2652 and TLC2652A an ideal choice for

low-level signal processing applications such as

strain gauges, thermocouples, and other

transducer amplifiers. For applications that

require extremely low noise and higher usable

bandwidth, use the TLC2654 or TLC2654A

device, which has a chopping frequency of

10 kHz.

The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior

performance in either single-supply or split-supply applications, even at power supply voltage levels as low as

±1.9 V.

Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry

is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible

to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the

clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply

configuration with a normal CMOS or TTL clock input.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinCMOS is a trademark of Texas Instruments.

DD+

OUT

CLAMP

D008, JG, OR P PACKAGE

NC − No internal connection

INT/EXT

CLK IN

CLK OUT

DD+

OUT

CLAMP

C RETURN

D014, J, OR N PACKAGE

(TOP VIEW)

3212019

910111213

CLK OUT

DD+

OUT

FK PACKAGE

(TOP VIEW)

INT/EXT

CLAMP

CLK IN

C RETURN

DD−

(TOP VIEW)

IN−

IN+

IN−

IN+

DD−

IN−

IN+

DD−

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Summary of content (39 pages)

PAGE 1
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 D Extremely Low Offset Voltage . . . 1 µV Max D Extremely Low Change on Offset Voltage D008, JG, OR P PACKAGE (TOP VIEW) With Temperature . . . 0.003 µV/°C Typ CXA IN − IN + VDD − D Low Input Offset Current D D D D D D 500 pA Max at TA = − 55°C to 125°C AVD . . . 135 dB Min CMRR . . . 120 dB Min kSVR . . .
PAGE 2
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 description (continued) Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload recovery time. If desired, an output clamp pin is available to reduce the recovery time even further. The device inputs and output are designed to withstand ± 100-mA surge currents without sustaining latch-up.
PAGE 3
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TLC2652Y chip information This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
PAGE 4
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage VDD + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Supply voltage VDD − (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† TLC2652C MIN 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) TYP 0.
PAGE 6
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics specified free-air temperature, VDD± = ±5 V PARAMETER TEST CONDITIONS TA† 25°C TLC2652C MIN TYP 2 2.8 TLC2652AC MAX MIN TYP 2 2.8 MAX SR + Positive slew rate at unity gain SR − Negative slew rate at unity gain VO = ± 2.
PAGE 7
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLC2652I MIN TYP 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) 0.
PAGE 8
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD ± = ±5 V PARAMETER TEST CONDITIONS TA† 25°C TLC2652I MIN TYP 2 2.8 TLC2652AI MAX MIN TYP 2 2.8 MAX SR + Positive slew rate at unity gain SR − Negative slew rate at unity gain VO = ± 2.
PAGE 9
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLC2652Q TLC2652M MIN VIO Input offset voltage (see Note 7) αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) 25°C TYP MAX 0.6 3.
PAGE 10
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD ± = ±5 V PARAMETER TEST CONDITIONS TA† 25°C SR + Positive slew rate at unity gain SR − Negative slew rate at unity gain Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In φm VO = ± 2.3 V, RL = 10 kΩ, CL = 100 pF MIN TYP 2 2.8 Full range 1.
PAGE 11
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at VDD± = ±5 V, TA = 25°C (unless otherwise noted) PARAMETER VIO TEST CONDITIONS TLC2652Y MIN Input offset voltage Input offset voltage long-term drift (see Note 4) VIC = 0, RS = 50 Ω UNIT TYP MAX 0.6 3 0.003 0.
PAGE 12
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Normalized input offset voltage vs Chopping frequency 1 IIB Input bias current vs Common-mode input voltage vs Chopping frequency vs Free-air temperature 2 3 4 IIO Input offset current vs Chopping frequency vs Free-air temperature 5 6 Clamp current vs Output voltage 7 Maximum peak-to-peak output volt
PAGE 13
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† NORMALIZED INPUT OFFSET VOLTAGE vs CHOPPING FREQUENCY INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE 70 IIB I IB − Input Bias Current − pA 60 VIO uV VIO − Normalized Input Offset − µ V 25 VDD ± = ± 5 V VIC = 0 TA = 25°C 50 40 30 20 10 VDD ± = ± 5 V TA = 25°C 20 15 10 5 0 −10 100 1k 10 k Chopping Frequency − Hz 0 −5 100 k −4
PAGE 14
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† INPUT OFFSET CURRENT vs CHOPPING FREQUENCY INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 10 VDD ± = ± 5 V VIC = 0 VDD ± = ± 5 V VIC = 0 TA = 25°C 20 IIIO IO − Input Offset Current − pA IIIO IO − Input Offset Current − pA 25 15 10 5 8 6 4 2 0 0 100 1k 10 k 105 45 65 85 TA − Free-Air Temperature − °C 25 100 k Chopping Freq
PAGE 15
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT 7.5 VDD ± = ± 5 V TA = 25°C 4.8 VOM + VDD ± = ± 7.5 V TA = 25°C |VOM| |VOM − Maximum Peak Output Voltage − V |VOM| |VOM − Maximum Peak Output Voltage − V 5 VOM − 4.6 4.4 4.2 7.3 7.1 6.9 4 6.7 0 0.4 0.8 1.2 1.6 2 0 0.
PAGE 16
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 120 60° ÁÁ ÁÁ ÁÁ Phase Shift 80° 80 100° AVD 60 120° 40 140° 20 160° 0 −20 −40 10 180° VDD ± = ± 5 V RL = 10 kΩ CL = 100 pF TA = 25°C 100 Phase Shift AVD AVD− Large-Signal Differential Voltage Amplification − dB 100 200° 1k 10 k 100 k 1M 220
PAGE 17
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† CHOPPING FREQUENCY vs FREE-AIR TEMPERATURE CHOPPING FREQUENCY vs SUPPLY VOLTAGE 460 540 VDD ± = ± 5 V TA = 25°C 450 Chopping Frequency − kHz Chopping Frequency − kHz 520 500 480 460 440 430 420 410 440 400 −75 420 0 1 6 2 3 4 5 |VDD ±| − Supply Voltage − V 7 8 75 100 0 25 50 −50 −25 TA − Free-Air Temperature − °C Figu
PAGE 18
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE 15 VO = 0 TA = 25°C IOS I OS − Short-Circuit Output Current − mA IOS I OS − Short-Circuit Output Current − mA 12 8 4 VID = − 100 mV 0 −4 −8 VID = 100 mV −12 0 1 6 2 3 4 5 |VDD ±| − Supply Voltage − V 7 10 5 VID = − 100 mV 0
PAGE 19
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 100 4 75 3 50 2 VO VO − Output Voltage − V VO VO − Output Voltage − mV VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE VDD ± = ± 5 V RL = 10 kΩ CL = 100 pF TA = 25°C 25 0 −25 −50 VDD ± = ± 5 V RL = 10 kΩ CL = 100 pF TA = 25°C 1 0 −1 −2 −3 −75 −100 0 1 2 3 4 5 6 −4 7 0 Figure
PAGE 20
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 100 2.1 80 Gain-Bandwidth Product − MHz V Vn nV/HzHz n − Equivalent Input Noise Voltage − nV/ EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 60 40 20 VDD ± = ± 5 V RS = 20 Ω TA = 25°C 0 1 10 100 RL = 10 kΩ CL = 100 pF TA = 25°C 2 1.9 1.
PAGE 21
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† PHASE MARGIN vs LOAD CAPACITANCE PHASE MARGIN vs FREE-AIR TEMPERATURE 50° 60° 50° om φ m − Phase Margin om φ m − Phase Margin 48° 46° 44° 42° VDD ± = ± 5 V RL = 10 kΩ TA = 25°C 30° 20° 10° VDD ± = ± 5 V RL = 10 kΩ CL = 100 pF 40° −75 −50 −25 40° 0° 0 25 50 75 100 125 0 200 TA − Free-Air Temperature − °C 400 600
PAGE 22
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION internal/external clock When large differential input voltage conditions are applied to the TLC2652, the nulling loop attempts to prevent the output from saturating by driving CXA and CXB to internally-clamped voltage levels. Once the overdrive condition is removed, a period of time is required to allow the built-up charge to dissipate.
PAGE 23
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION latch-up avoidance Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible.
PAGE 24
 SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION theory of operation (continued) During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC2652AI-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2652AI-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652C-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652I-8DR SOIC D 8 2500 340.5 338.1 20.
PAGE 32
MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.