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SLAS345 − DECEMBER 2001

    

     

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FEATURES

200-KSPS Sampling Rate

D Built-In Conversion Clock

D INL: ±1 LSB Max

DNL: ±1 LSB Max

D SINAD = 81.5 dB, SFDR = 95 dB

THD = 94 dB at 15 kHz f

, 200 KSPS

D SPI/DSP-Compatible Serial Interfaces With

SCLK Input up to 15 MHz

D Single 5-V Supply

D Rail-to-Rail Analog Input With 500 kHz BW

D Two Input Options Available:

− TLC3541 − Single Channel Input

− TLC3545 − Single Channel,

Pseudo-Differential Input

D (TLC3541) Optimized DSP Interface −

Requires FS Input Only

D Low Power With Auto-Power Down

− Operating Current: 3.5 mA

− Auto-Powerdown Current: 5 µA

D Pin Compatible 12-/14-/16-Bit Family in 8-Pin

SOIC and MSOP Packages

APPLICATIONS

ATE System

D Industrial Process Control

D Measurement

D Motor Control

DESCRIPTION

The TLC3541 and TLC3545 are a family of high

performance, 14-bit, low power, miniature CMOS

analog-to-digital converters (ADCs). These devices

operate from a single 5-V supply. Devices are available

with single, dual, or single pseudo-differential inputs. All

of these devices have a chip select (CS

), serial clock

(SCLK), and serial data output (SDO) that provides a

direct 3-wire interface to the serial port of most popular

host microprocessors (SPI interface). When interfaced

with a DSP, a frame sync signal (FS) is used to indicate

the start of a serial data frame on either pin 1 (CS

) or pin

7 (FS) for the TLC3541. The TLC3545 ADC connects

to the DSP via pin 1 only (CS

The TLC3541 and TLC3545 are designed to operate

with low power consumption. The power saving feature

is further enhanced with an auto-power down mode.

This product family features a high-speed serial link to

modern host processors with an external SCLK up to

15 MHz. Both families use a built-in oscillator as the

conversion clock, providing a 2.67 µs maximum

conversion time.

SDO

SCLK

REF

GND

AIN

TLC3541

D OR DGK Package

(TOP VIEW)

SDO

SCLK

AIN(−)

REF

GND

AIN(+)

TLC3545

D OR DGK Package

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (26 pages)

PAGE 1
SLAS345 − DECEMBER 2001 FEATURES D 200-KSPS Sampling Rate D Built-In Conversion Clock D INL: ±1 LSB Max D D D D D D D D DNL: ±1 LSB Max SINAD = 81.
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SLAS345 − DECEMBER 2001 AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C to 85°C 8-MSOP (DGK) 8-SOIC (D) TLC3541IDGK (PKG Code = AMG) TLC3541ID TLC3545IDGK (PKG Code = AMM) TLC3545ID functional block diagram TLC3541 TLC3545 VDD VDD REF AIN REF S/H OSC SCLK CS FS LOW POWER SAR ADC AIN (+) SDO AIN (−) OSC Conversion Clock CONTROL LOGIC SCLK CS LOW POWER SAR ADC Conversion Clock CONTROL LOGIC GND GND 2 S/H www.ti.
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SLAS345 − DECEMBER 2001 Terminal Functions TLC3541 single channel unipolar ADCs TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a maximum delay time. If the TLC3541 is attached to a dedicated TMS320 DSP serial port using the FS input, CS can be grounded. FS 7 I DSP frame sync input. Indication of a start of a serial data frame.
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SLAS345 − DECEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLAS345 − DECEMBER 2001 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS TYP MAX VDD = 4.5 V, VDD = 4.5 V IOH = −0.2 mA IOL = 0.8 mA Off-state output current (high-impedance-state) VO = VDD, VO = 0, CS = VDD 1 2.5 CS = VDD −1 −2.5 IIH IIL High-level input current 0.005 2.5 Low-level input current VI = VDD VI = 0 −0.005 2.
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SLAS345 − DECEMBER 2001 timing requirements, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified) MIN TYP MAX UNIT tcyc(SCLK) tw1 SCLK cycle time, VDD = 4.5 V to 5.
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SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS FFT 0 fi = 15 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 70 80 90 100 70 80 90 100 fi − Input Frequency − kHz Figure 1 FFT 0 fi = 1.5 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 fi − Input Frequency − kHz DNL − Differential Nonlinearity − LSB Figure 2 DIFFERENTIAL NONLINEARITY 1.5 1 0.5 0 −0.
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SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY 1.5 1 0.5 0 −0.5 −1 −1.
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SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 83.4 83.3 −84 SNR − Signal-To-Noise Ration − dB THD − Total Harmonic Distortion − dB −82 −86 fi = 100 kHz −88 −90 −92 fi = 15 kHz −94 83.1 fi = 15 kHz 83 82.9 82.8 82.7 82.6 −96 fi = 1 kHz −98 82.
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SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS MINIMUM DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 0.8 0.8 0.6 0.6 Minimum Differential Nonlinearity − LSB Maximum Differential Nonlinearity − LSB MAXIMUM DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 4.0 4.0 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 4.0 4.0 5.0 5.0 4.5 0.4 VREF − Reference Voltage − V 4.5 VREF − Reference Voltage − V Figure 11 Figure 12 INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 0.
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SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing device initialization/RESET cycle The TLC3541/45 each require one RESET cycle after power-on for initialization in order to operate properly. The RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS high.
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SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing (continued) sampling and conversion cycle TLC3541: Control via pin 1, CS (FS = 1 at the falling edge of CS) − The falling edge of CS is the start of the cycle. Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK.
PAGE 13
SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control via pin 1 (CS, DSP interface) All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC3541 in this configuration, the FS input is tied to VDD.) Enough time should be allowed before the next rising CS edge so that the conversion cycle is not terminated prematurely.
PAGE 14
SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION 1 SCLK tconv ts tcyc(SCLK) 5 2 14 16 15 1 17, 24 tw1 tsu1 t(PWRDWN) th2 tw2 CS th1 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td2 SDO tw3 td3 LSB MSB td1 MSB LSB−2 LSB−1 Figure 18. Critical Timing: Control Via CS Input (FS = 1 for TLC3541) tconv ts 2 1 SCLK 5 15 14 tsu5 16 t(PWRDWN) th2 th4 1 17, 24 tsu4 CS tw4 t(PWRDWN) td2 FS ÎÎÎ ÎÎÎ tsu3 SDO ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td3 LSB MSB td4 LSB−1 LSB−2 Figure 19.
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SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION 2 1 SCLK 8 th7 9 2 1 tsu7 th7 8 9 2 1 tsu6 tcyc(reset) CS tcyc(reset) OR Normal Cycle Begins FS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Initialization Cycle (Reset) SDO MSB MSB ÎÎÎ ÎÎÎ MSB Figure 21. Critical Timing: Initialization Cycle (TLC3541 Only) MSB−1 detailed description The TLC3541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22 shows a simplified version of the ADC.
PAGE 16
SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION pseudo-differential inputs The TLC3545 operates in pseudo-differential mode. The inverted input is available on pin 5. The inverted input can tolerate a maximum input ripple of ±0.2 V. It is normally used for zero-scale offset cancellation or ground noise rejection. serial interface Output data format is binary (unipolar straight binary).
PAGE 17
SLAS345 − DECEMBER 2001 APPLICATION INFORMATION 5V DSP to Single TLC3541 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ VDD FS FSX0 SD0 DR0 DSP TLC3541 CLKX0 SCLK CLKR0 CS REF AIN GND 5V DSP to Single TLC3545 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ FSX0 CS DR0 SD0 DSP SCLK CLKX0 CLKR0 VDD REF TLC3545 AIN(+) AIN(−) GND DSP to Multiple TLC3541s XF0 FSX0 DR0 DSP CLKX0 CLKR0 XF1 EXT REF INPUT 5V REF 0.1 µF 5V 0.1 µF 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC3541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLC3541IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC3545IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3541IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLC3541IDR SOIC D 8 2500 367.0 367.0 35.0 TLC3545IDR SOIC D 8 2500 367.0 367.0 35.
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