TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 D 14-Bit Resolution D Maximum Throughput 200 KSPS D Analog Input Range 0-V to Reference D D D D D D D D D D D D D Voltage Multiple Analog Inputs: – 8 Channels for TLC3548 – 4 Channels for TLC3544 Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces With SCLK up to 25 MHz Single 5-V Analog Supply;
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 description (continued) In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 equivalent input circuit VDD MUX 1.1 kΩ Max Ain VDD Ron C(sample) = 30 pF Max Digital Input REFM Diode Turn on Voltage: 35 V Equivalent Digital Input Circuit Equivalent Analog Input Circuit Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION 9 10 11 12 13 14 15 16 I Analog signal inputs.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 Terminal Functions (Continued) TERMINAL NO. NAME EOC(INT) I/O TLC3544 TLC3548 4 4 O DESCRIPTION End of conversion (EOC) or interrupt to host processor (INT) EOC: used in conversion mode 00 only.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4 V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4 V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) DVDD SCLK, SDI, SDO, EOC and INT PARAMETERS MIN DVDD = 2.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 VIH 90% 50% 10% CS VIL tc(1) tw(1) 1 SCLK 16 th(1) tsu(1) SDI Don’t Care ID15 ID1 Don’t Care ID0 td(1) th(2) SDO Hi-Z OD15 OD1 Hi-Z OD0 td(2) See Note A tr(1) EOC tf(1) OR td(3) See Note B INT tf(1) tr(1) NOTES: A.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CS trigger PARAMETERS MIN TYP MAX tsu(2) td(4) Setup time, CS falling edge before SCLK rising edge, at 25-pF load Delay time,
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) FS trigger PARAMETERS MIN td(8) tsu(3) Delay time, delay from CS falling edge to FS rising edge, at 25-pF load tw(3) Pulse wi
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CSTART trigger PARAMETERS MIN TYP MAX UNIT 0 15 21 ns td(12) Delay time, delay from CSTART rising edge to EOC falling ed
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) Charge Redistribution DAC _ Ain + Control Logic ADC Code REFM Figure 5. Simplified Block Diagram of the Successive-Approximation System analog input range and internal test voltages TLC3548 has eight analog inputs (TLC3544 has four) and three test voltages.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 analog input mode (continued) Single Ended X8† X4‡ A0 A0 A1 A1 A2 A2 A3 A3 X A4 X A5 X A6 X A7 Analog MUX Pseudodifferential SAR ADC X8† A0(+) A1(–) A2(+) A3(–) A4(+) A5(–) A6(+) A7(–) Pair A Pair B X4‡ A0(+) Pair A A1(–) A2(+) Pair B A3(–) Pair C Analog MUX SAR ADC Pair D † TLC3548 ‡ TLC3544 Figure 7.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) 2s Complement BTC 01111111111111 Binary USB 11111111111111 01111111111110 11111111111110 16383 01111111111101 11111111111101 16382 16381 00000000000001 10000000000001 8193 00000000000000 10000000000000 8192 11111111111111 01111111111111 8191 10000000000010 0000000
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) operation description The converter samples the selected analog input signal, then converts the sample into digital output, according to the selected output format.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) command period After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI, SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data, ID[15:12], are shifted in and decoded.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) Table 2.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 sampling period (continued) Normal Long Sampling Mode: This mode is the same as normal short sampling, except that it lasts 44 SCLK periods. Extended Sampling Mode: The external trigger signal, CSTART, triggers sampling and conversion. SCLK is not used for sampling.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion mode (continued) Sweep Mode (Mode 10): During each operation, all of the channels listed in the sweep sequence (D[4:3] of the CFR register) are sampled and converted at one time according to the programmed sequence. The results are stored in the FIFO.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation cycle timing CS Initiates Operation 12 SCLKs for Short 44 SCLKs for Long 4 SCLKs t(setup)† SDI 18 OSC for Internal OSC† 72 SCLK for External Clock 15 ns t(convert) t(overhead) t(sample) 4-bit Command 12-bit CFR Data (Optional) SDO 14-bit Data (Previous Conversion) 2-bit Don’t Care Active CS (F
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation cycle timing (continued) Table 3. Operation Options CONVERSION IS INITIATED BY MODE CS FS CSTART 00 1. Issue new Select/Read operation to read data and start new conversion. 2. Reconfigure the device. 1. Issue new Select/Read operation to read data and start new conversion. 2.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation timing diagrams (continued) 1 2 3 4 5 6 12 7 13 14 15 16 CS ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ FS = High SDI ID15 1D14 ID13 1D12 ID11 ID10 ID9 ID4 ID3 ID2 ID1 ID0 INT OR 1 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌ EOC SDO Note: Hi-Z Signal May Not Exist.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation 48 SCLKs for Long Sampling 16 SCLKs for Short Sampling 1 2 3 4 CS ÌÌÌ ÌÌ ÌÌÌ ÌÌ FS in High SDI Select Channel ID15 ID14 ID13 1D12 INT 5 6 7 12 13 14 15 1 16 ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌ ID15 t(SAMPLE) EOC t(conv) Previous Conversion
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Select Channel 16 SCLK Select Channel 16 SCLK t(sample) CS Tied to Low CSTART Possible Signal FS t(convert) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ** *** SDI ** INT EOC OR SDO ÌÌ ÌÌ ** Data Lost Previous Conversion Result Hi-Z Conversion Result Hi-Z Hi-Z Possible Signal S
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH3 Conversion From CH0 Conversion From CH3 CS ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ FS SDI ** *** ** ** ** * * * ** * ** ** ** * INT Hi-Z SDO CH0 1st Sweep CH1 ** *
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH2 Conversion From CH0 Conversion From CH2 CS FS CSTART Ì ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ ÌÌ *** ** SDI INT 1st SWEEP SDO * * * * CH0 CH0 CH2 CH2 ** * REPEAT 1st FIFO Read Don’t Care *** ** * CH0 2nd FIFO
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 FIFO operation (continued) The device has an 8-level FIFO that can be programmed for different thresholds. An interrupt is sent to the host after the preprogrammed threshold is reached.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 1.0 Internal Reference = 4 V AVDD = 5 V, TA = 25°C 0.5 0.0 –0.5 –1.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS INL AND DNL vs FREE-AIR TEMPERATURE ZERO OFFSET AND GAIN ERROR (LSB) vs FREE-AIR TEMPERATURE 1.0 4 Internal Reference = 4 V AVDD = 5 V 2 Zero Offset and Gain Error – LSB 0.8 INL (LSB) 0.7 0.6 DNL (LSB) 0.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS SINAD vs INPUT SIGNAL FREQUENCY ENOB vs INPUT SIGNAL FREQUENCY 90 14.0 External Reference = 4 V AVDD = 5 V TA = 25°C External Reference = 4 V AVDD = 5 V TA = 25°C 13.5 ENOB – Bits SINAD – dB 85 80 75 13.0 12.5 70 12.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT AT SOFTWARE POWER-DOWN vs FREE-AIR TEMPERATURE ICC – Supply Current at Software Power Down– µA SUPPLY CURRENT vs FREE-AIR TEMPERATURE 4.5 4.3 4.2 4.1 4.0 3.
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 APPLICATION INFORMATION interface with host Figure 34 shows examples of the interface between a single converter and a host DSP (TMS320C54x DSP) or microprocessor.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2008 Orderable Device Status (1) Package Type Package Drawing TLC3548IPWRG4 ACTIVE TSSOP PW Pins Package Eco Plan (2) Qty 24 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC3544CPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TLC3548CPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TLC3548IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3544CPWR TSSOP PW 20 2000 367.0 367.0 38.0 TLC3548CPWR TSSOP PW 24 2000 367.0 367.0 38.0 TLC3548IPWR TSSOP PW 24 2000 367.0 367.0 38.
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