Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Comparator Multi-purpose CMOS, Push pull, TTL SOIC 8



    



SGLS127 − JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−55°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product Change Notification

D Qualification Pedigree

†

D Push-Pull CMOS Output Drives Capacitive

Loads Without Pullup Resistor,

= ± 8 mA

D Very Low Power . . . 100 µW Typ at 5 V

D Fast Response Time ...t

PLH

= 2.7 µs Typ

With 5-mV Overdrive

D Single-Supply Operation ...4 V to 16 V

D On-Chip ESD Protection

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

description

The TLC3702 consists of two independent micropower voltage comparators designed to operate from a single

supply and be compatible with modern HCMOS logic systems. They are functionally similar to the LM339 but

use one-twentieth of the power for similar response times. The push-pull CMOS output stage drives capacitive

loads directly without a power-consuming pullup resistor to achieve the stated response time. Eliminating the

pullup resistor not only reduces power dissipation, but also saves board space and component cost. The output

stage is also fully compatible with TTL requirements.

Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes.

Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and

low bias currents, the LinCMOS process offers extremely stable input offset voltages with large differential

input voltages. This characteristic makes it possible to build reliable CMOS comparators.

ORDERING INFORMATION

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−55°C to 125°C SOP − D Tape and reel TLC3702MDREP 3702ME

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated.

D PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

GND

2OUT

2IN−

2IN+

OUT

symbol (each comparator)

IN+

IN−

Summary of content (30 pages)

PAGE 1
 SGLS127 − JULY 2002 D Controlled Baseline D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Push-Pull CMOS Output Drives Capacitive Loads Without Pullup Resistor, IO = ± 8 mA Very Low Power . . . 100 µW Typ at 5 V Fast Response Time . . . tPLH = 2.
PAGE 2
 SGLS127 − JULY 2002 functional block diagram (each comparator) VDD IN+ Differential Input Circuits OUT IN− GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
 SGLS127 − JULY 2002 electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA −55°C to 125°C VIO Input offset voltage VDD = 5 V to 10 V, VIC = VICRmin, See Note 3 IIO Input offset current VIC = 2.5 V MIN 25°C 1.2 125°C VIC = 2.
PAGE 4
 SGLS127 − JULY 2002 switching characteristics, VDD = 5 V, TA = 25°C PARAMETER tPLH tPHL TEST CONDITIONS Propagation delay time, low-to-high-level output† Propagation delay time, high-to-low-level output† tf Fall time tr Rise time f = 10 kHz, CL = 50 pF TYP Overdrive = 2 mV 4.5 Overdrive = 5 mV 2.7 Overdrive = 10 mV 1.9 Overdrive = 20 mV 1.4 Overdrive = 40 mV 1.1 VI = 1.4 V step at IN+ Overdrive = 2 mV 1.1 Overdrive = 5 mV 2.
PAGE 5
 SGLS127 − JULY 2002 PRINCIPLES OF OPERATION LinCMOS process The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
PAGE 6
 SGLS127 − JULY 2002 PRINCIPLES OF OPERATION input protection circuit operation Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. positive ESD transients Initial positive charged energy is shunted through Q1 to VSS.
PAGE 7
 SGLS127 − JULY 2002 PRINCIPLES OF OPERATION circuit-design considerations (continued) INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 8 10 TA = 25° C TA = 25° C 9 7 8 I I − Input Current − mA I I − Input Current − mA 6 5 4 3 2 7 6 5 4 3 2 1 1 0 VDD VDD + 4 VDD + 8 VDD + 12 0 VDD − 0.3 VDD − 0.5 VDD − 0.7 VDD − 0.
PAGE 8
 SGLS127 − JULY 2002 PARAMETER MEASUREMENT INFORMATION The TLC3702 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo loop which is designed to force the device output to a level within this linear region.
PAGE 9
 SGLS127 − JULY 2002 PARAMETER MEASUREMENT INFORMATION VDD IC1a 1/4 TLC274CN + Buffer C2 1 µF R6 1 MΩ − R4 47 kΩ − VIO (X100) + IC1b 1/4 TLC274CN Integrator C4 0.1 µF − Triangle Generator R9 100 Ω 1% R3 100 Ω + R7 1.8 kΩ 1% R1 240 kΩ + IC1c 1/4 TLC274CN DUT − C1 0.1 µF C3 0.68 µF R5 1.8 kΩ 1% R8 10 kΩ 1% R2 10 kΩ Figure 6.
PAGE 10
 SGLS127 − JULY 2002 PARAMETER MEASUREMENT INFORMATION VDD Pulse Generator 1 µF 50 Ω + 1V DUT 10 Ω 10-Turn Potentiometer − 1 kΩ CL (see Note A) 0.1 µF −1V TEST CIRCUIT Overdrive Overdrive Input Input 100 mV 100 mV 90% Low-to-High Level Output 90% High-to-Low Level Output 50% 10% 50% 10% tf tr tPHL tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 7.
PAGE 11
 SGLS127 − JULY 2002 TYPICAL CHARACTERISTICS† Table of Graphs FIGURE VIO IIB Input offset voltage Distribution 8 Input bias current vs Free-air temperature 9 CMRR Common-mode rejection ratio vs Free-air temperature 10 kSVR Supply-voltage rejection ratio vs Free-air temperature 11 VOH High-level output current vs Free-air temperature vs High-level output current 12 13 VOL Low-level output voltage vs Low-level output current vs Free-air te
PAGE 12
 SGLS127 − JULY 2002 TYPICAL CHARACTERISTICS† SUPPLY VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE 90 90 88 k SVR − Supply Voltage Rejection Ratio − dB CMRR − Common-Mode Rejection Ratio − dB COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE VDD = 5 V 86 84 82 80 78 76 74 72 70 −75 −50 −25 0 25 50 75 100 88 VDD = 5 V to 10 V 86 84 82 80 78 76 74 72 70 −75 125 −50 −25 TA − Free-Air Temperature − °C 50 75 100 5 VDD VOH − High-Inp
PAGE 13
 SGLS127 − JULY 2002 TYPICAL CHARACTERISTICS† LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.5 400 3V VOL − Low-Level Output Voltage − mV VOL − Low-Level Output Voltage − V TA = 25°C 4V 1.25 5V 1 0.75 10 V 0.5 0.
PAGE 14
 SGLS127 − JULY 2002 TYPICAL CHARACTERISTICS LOW-TO-HIGH-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 5 VO − Output Voltage − V 40 mV 20 mV 10 mV 5 mV 2 mV VO − Output Voltage − V 40 mV 20 mV 10 mV 5 mV 2 mV 0 0 100 100 Differential Input Voltage − mV Differential Input Voltage − mV HIGH-TO-LOW-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES VDD = 5 V TA = 25°C CL = 50 pF 0 0 1 2 3 4 VDD = 5 V TA = 25° C CL = 50 pF 0 5 0 t
PAGE 15
 SGLS127 − JULY 2002 TYPICAL CHARACTERISTICS† AVERAGE SUPPLY CURRENT (PER COMPARATOR) vs FREQUENCY SUPPLY CURRENT vs SUPPLY VOLTAGE 40 10000 Outputs Low No Loads 35 VDD = 16 V 1000 VDD − Supply Current − µ A VDD − Supply Current − µ A TA = 25°C CL = 50 pF 10 V 5V 100 4V TA = − 55°C TA = − 40°C 30 25 TA = − 25°C 20 15 TA = − 125°C TA = 85°C 10 5 3V 10 0.01 0 0.
PAGE 16
 SGLS127 − JULY 2002 APPLICATION INFORMATION The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range.
PAGE 17
 SGLS127 − JULY 2002 APPLICATION INFORMATION 5V VCC 12 V 12-V Sense 3.3 kΩ SENSE 10 kΩ 1/2 TLC3702 + TL7705A RESIN 1 kΩ 5V RESET To µP Reset − REF CT GND 2.5 V 1 µF CT (see Note B) 1/2 TLC3702 + V(UNREG) (see Note A) To µP Interrupt Early Power Fail R1 − R2 Monitors 5 VDC Rail Monitors 12 VDC Rail Early Power Fail Warning (R1 +R2) R2 B. The value of CT determines the time delay of reset. NOTES: A. V (UNREG) + 2.5 Figure 26.
PAGE 18
 SGLS127 − JULY 2002 APPLICATION INFORMATION 12 V 12 V R1 100 kΩ (see Note B) 12 V − − R2 5 kΩ (see Note C) 1/2 TLC3702 100 kΩ 1OUT + + 22 kΩ 100 kΩ − C1 0.01 µF (see Note A) 100 kΩ R3 100 kΩ (see Note B) 1OUT 2OUT NOTES: A. Adjust C1 for a change in oscillator frequency where: 1/f = 1.85(100 kΩ)C1 B. Adjust R1 and R3 to change duty cycle C. Adjust R2 to change deadtime Figure 27.
PAGE 19
 SGLS127 − JULY 2002 APPLICATION INFORMATION V + 6 V to 16 V I I + 0.01 mA to 0.25 mA L (R1 ) R2) V + 2.5 O R2 1/2 TLC3702 + SK9504 (see Note C) G S 100 kΩ − 100 kΩ VI VI 1/2 TLC3702 + − 100 kΩ D + C1 180 µF (see Note A) VI 47 µF Tantalum IN5818 100 kΩ R1 R=6Ω L = 1 mH (see Note D) VO 100 kΩ TLC271 (see Note B) VI 470 µF RL + R2 100 kΩ − C2 100 pF 100 kΩ 270 kΩ VI LM385 2.5 V NOTES: A. Adjust C1 for a change in oscillator frequency B.
PAGE 20
 SGLS127 − JULY 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−ā 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC3702MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03643-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC3702MDREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3702MDREP SOIC D 8 2500 346.0 346.0 29.
PAGE 24
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC3702MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03643-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC3702MDREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3702MDREP SOIC D 8 2500 367.0 367.0 35.
PAGE 28
PAGE 29
PAGE 30
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.