Datasheet

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TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-Bit Resolution A/D Converter

Microprocessor Peripheral or Stand-Alone

Operation

On-Chip 12-Channel Analog Multiplexer

Built-In Self-Test Mode

Software-Controllable Sample and Hold

Total Unadjusted Error ... ±0.5 LSB Max

Direct Replacement for Motorola

MC145041

Onboard System Clock

End-of-Conversion (EOC) Output

Pinout and Control Signals Compatible

With the TLC1542/3 10-Bit A/D Converters

CMOS Technology

PARAMETER VALUE

Channel Acquisition/Sample Time 16 µs

Conversion Time (Max) 20 µs

Samples per Second (Max) 25 × 10

3

Power Dissipation (Max) 10 mW

description

The TLC542 is a CMOS converter built around an

8-bit switched-capacitor successive-approximation

analog-to-digital converter. The device is designed

for serial interface to a microprocessor or peripheral

via a 3-state output with three inputs [including I/O

CLOCK, CS

(chip select), and ADDRESS INPUT].

The TLC542 allows high-speed data transfers and

sample rates of up to 40,000 samples per second. In addition to the high-speed converter and versatile control

logic, an on-chip 12-channel analog multiplexer can sample any one of 11 inputs or an internal self-test voltage,

and the sample and hold is started under microprocessor control. At the end of conversion, the end-of-

conversion (EOC) output pin goes high to indicate that conversion is complete.

The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate

ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switched-

capacitor design allows low-error (±0.5 LSB) conversion in 20 µs over the full operating temperature range.

The TLC542C is characterized for operation from 0°C to 70°C and the TLC542I is characterized for operation

from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

CHIP CARRIER

(FN)

PLASTIC DIP

(N)

SMALL OUTLINE

(DW)

0°C to 70°C — TLC542CN TLC542CDW

–40°C to 85°C TLC542IFN TLC542IN TLC542IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2001, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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INPUT A0

INPUT A1

INPUT A2

INPUT A3

INPUT A4

INPUT A5

INPUT A6

INPUT A7

INPUT A8

GND

V

CC

EOC

I/O CLOCK

ADDRESS INPUT

DATA OUT

CS

REF+

REF–

INPUT A10

INPUT A9

DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

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I/O CLOCK

ADDRESS INP

U

DATA OUT

CS

REF+

INPUT A3

INPUT A4

INPUT A5

INPUT A6

INPUT A7

FN PACKAGE

(TOP VIEW)

INPUT A2

INPUT A1

INPUT A0

INPUT A10

REF–

V

EOC

INPUT A8

GND

INPUT A9

CC

Summary of content (12 pages)

PAGE 1
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 D D D D D D D D D DW OR N PACKAGE (TOP VIEW) 8-Bit Resolution A/D Converter Microprocessor Peripheral or Stand-Alone Operation On-Chip 12-Channel Analog Multiplexer Built-In Self-Test Mode Software-Controllable Sample and Hold Total Unadjusted Error . . . ± 0.
PAGE 2
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 functional block diagram REF+ 8-Bit Analog-to-Digital Converter (Switched-Capacitors) Sample and Hold 8 12-Channel Analog Multiplexer Analog Inputs REF– 4 Output Data Register Input Address Register 8 8-to-1 Data Selector and Driver DATA OUT 4 Self-Test Reference 4 Input Multiplexer ADDRESS INPUT Control Logic and I/O Counters 2 I/O CLOCK CS EOC typical equiv
PAGE 3
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 operating sequence 1 2 3 4 5 6 7 8 I/O CLOCK 1 2 3 4 5 6 7 8 Don’t Care Access Cycle B (see Note A) tsu(A) tacq Access Cycle C tc(1) t(acq) 12 Internal System Clocks ≤ 12 µs tsu(CS) CS MSB ADDRESS INPUT B3 LSB B2 B1 MSB Don’t Care B0 C3 LSB C2 C1 Don’t Care C0 Hi-Z State Hi-Z State DATA OUT A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B
PAGE 4
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 recommended operating conditions, VCC = 4.75 to 5.5 V MIN NOM MAX 4.75 5 5.5 V Vref– – 0.1 VCC 0 VCC + 0.
PAGE 5
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 operating characteristics over recommended operating free-air temperature range, VCC = Vref + = 4.75 to 5.5 V, f(clock I/O) = 1 MHZ PARAMETER EL EZS Linearity error (see Note 5) Zero-scale error (see Note 6) EFS Full-scale error (see Note 6) TEST CONDITIONS MIN TYP† MAX UNIT ±0.5 LSB See Note 2 ±0.5 LSB See Note 2 ±0.5 LSB ±0.
PAGE 6
TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION 1.4 V VCC 3 kΩ 3 kΩ Test Point Output Under Test Test Point Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR td, tr, AND tf Output Under Test Test Point CL (see Note A) 3 kΩ LOAD CIRCUIT FOR tPZH AND tPHZ LOAD CIRCUIT FOR tPZL AND tPLZ NOTE A: CL = 50 pF Figure 1. Load Circuits Address Valid 2V CS 0.
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TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION tr(I/O) tf(I/O) 2V 2V I/O CLOCK 0.8 V 0.8 V 0.8 V f(clock I/O) td(I/O-DATA) t(v) DATA OUT 2.4 V 2.4 V 0.4 V 0.4 V tr(bus), tf(bus) Figure 5. Data Output Timing I/O CLOCK 8th Clock 0.8 V td(I/O-EOC) 2.4 V EOC 0.4 V tf(EOC) Figure 6. EOC Timing tr(EOC) EOC 2.4 V 0.4 V td(EOC-DATA) 2.4 V DATA OUT 0.4 V Valid MSB Figure 7.
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TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 8, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by ( VC = VS 1– e – tc/RtCi ) (1) where Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS – (VS /51
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TLC542C, TLC542I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001 PRINCIPLES OF OPERATION The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. Three control inputs (I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-May-2009 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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