Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SO 24



SLAS105D − JANUARY 1995 − REVISED APRIL 2004

   

features

D 8-Bit Resolution

D Differential Linearity Error

− ± 0.3 LSB Typ, ± 1 LSB Max (25°C)

− ± 1 LSB Max

D Integral Linearity Error

− ± 0.6 LSB, ±0.75 LSB Max (25°C)

− ± 1 LSB Max

D Maximum Conversion Rate of

40 Megasamples Per Second (MSPS) Max

D Internal Sample and Hold Function

D 5-V Single Supply Operation

D Low Power Consumption ...85 mW Typ

D Analog Input Bandwidth ...≥75 MHz Typ

D Internal Reference Voltage Generators

applications

D Quadrature Amplitude Modulation (QAM)

and Quadrature Phase Shift Keying (QPSK)

Demodulators

D Digital Television

D Charge-Coupled Device (CCD) Scanners

D Video Conferencing

D Digital Set-Top Box

D Digital Down Converters

D High-Speed Digital Signal Processor Front

End

DGND

D1(LSB)

D8(MSB)

DDD

CLK

DGND

REFB

REFBS

AGND

ANALOG IN

DDA

REFT

REFTS

DDA

DDD

PW OR NS PACKAGE

(TOP VIEW)

AVAILABLE OPTIONS

−0°C to 70°C

SOP (NS)

TLC5540CNSLE

PACKAGE

TSSOP (PW)

TLC5540CPW

−40°C to 85°C

TLC5540INSLE

TLC5540IPW

description

The TLC5540 is a high-speed, 8-bit analog-to-digital converter (ADC) that converts at sampling rates up to 40

megasamples per second (MSPS). Using a semiflash architecture and CMOS process, the TLC5540 is able

to convert at high speeds while still maintaining low power consumption and cost. The analog input bandwidth

of 75 MHz (typ) makes this device an excellent choice for undersampling applications. Internal resistors are

provided to generate 2-V full-scale reference voltages from a 5-V supply, thereby reducing external

components. The digital outputs can be placed in a high impedance mode. The TLC5540 requires only a single

5-V supply for operation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

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Summary of content (23 pages)

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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PW OR NS PACKAGE (TOP VIEW) features D 8-Bit Resolution D Differential Linearity Error D D D D D D D OE DGND D1(LSB) D2 D3 D4 D5 D6 D7 D8(MSB) VDDD CLK − ±0.3 LSB Typ, ±1 LSB Max (25°C) − ±1 LSB Max Integral Linearity Error − ±0.6 LSB, ±0.
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www.ti.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 Terminal Functions TERMINAL NAME AGND NO. I/O 20, 21 DESCRIPTION Analog ground ANALOG IN 19 I Analog input CLK 12 I Clock input DGND 2, 24 D1 −D8 3 −10 O Digital data out. D1:LSB, D8:MSB 1 I Output enable. When OE = L, data is enabled. When OE = H, D1−D8 is high impedance.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 recommended operating conditions Supply voltage MIN NOM MAX VDDA −AGND VDDD −AGND 4.75 5 5.25 4.75 5 5.25 AGND −DGND −100 0 100 Reference input voltage (top), VI(REFT) VI(REFB)+1.8 0 Reference input voltage (bottom), VI(REFB) Analog input voltage range, VI(ANLG) (see Note 1) Full scale voltage, VI(REFT) − VI(REFB) High-level input voltage, VIH VI(REFB) 1.8 VI(REFB)+2 0.6 VDDA VI(REFT)−1.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 electrical characteristics at VDD = 5 V, VI(REFT) = 2.6 V, VI(REFB) = 0.6 V, fs = 40 MSPS, TA = 25°C (unless otherwise noted) TEST CONDITIONS† PARAMETER EL ED Linearity error, integral Linearity error, differential fs = 40 MSPS, VI = 0.6 V to 2.6 V Self bias (1), VRB Short REFB to REFBS Self bias (1), VRT Short REFT to REFTS Self bias (2), VRB Short REFB to AGND TYP MAX TA = 25°C TA = MIN to MAX MIN ± 0.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 operating characteristics at VDD = 5 V, VRT = 2.6 V, VRB = 0.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION tw(H) tw(L) CLK (Clock) ANALOG IN (Input Signal) D1 −D8 (Output Data) N+2 N+1 N N+4 N+3 N −3 N −2 N −1 N N+1 tpd Figure 1. I/O Timing Diagram Reference Level (2.5 V) OE Data Output Active tPHZ tPLZ Hi-Z VOH (4.5 V typical) Active tPZH tPZL VOL (0.4 V typical) Figure 2.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS POWER DISSIPATION vs SAMPLING FREQUENCY ANALOG INPUT BANDWIDTH 0.5 200 VDD = 5 V TA = 25°C 0 150 −1 −1.5 Gain − dB Power Dissipation − mW −0.5 100 −2 −2.5 −3 −3.5 50 −4 −4.5 −5 0.1 0 0 5 25 30 35 10 20 15 fs − Sampling Frequency − MHz 40 VCC = 5 V, VRT = 2.6 V, VRB = 0.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs AMBIENT TEMPERATURE DIFFERENTIAL NONLINEARITY 8 1 0.6 ENOB − Effective Number of Bits − BITS Differential Nonlinearity − LSB 0.8 VI = Vramp = 0.6 V − 2.6 V, 500 Hz VRT = 2.6 V, VRB = 0.6 V, VDD = 5 V fs = 40 MHz TA = 25°C 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 40 80 120 160 200 VDD = 5 V, VI = 1 V(PP), 3 MHz Sine Wave VRT = 2.6 V, VRB = 0.6 V, fs = 20 MHz 7.5 7 6.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 APPLICATION INFORMATION grounding and power supply considerations A signal ground is a low-impedance path for current to return to the source. Inside the TLC5540 A/D converter, the analog ground and digital ground are connected to each other through the substrate, which has a very small resistance (~30 Ω) to prevent internal latch-up.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PRINCIPLES OF OPERATION functional description The TLC5540 uses a modified semiflash architecture as shown in the functional block diagram. The four most significant bits (MSBs) of every output conversion result are produced by the upper comparator block CB1. The four least significant bits (LSBs) of each alternate output conversion result are produced by the lower comparator blocks CB-A and CB-B in turn (see Figure 12).
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PRINCIPLES OF OPERATION functional description (continued) The MSB comparator block converts on the falling edge of each applied clock cycle. The LSB comparator blocks CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The timing diagram of the conversion algorithm is shown in Figure 12.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PRINCIPLES OF OPERATION internal reference voltage conversion Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought out on terminals VDDA, REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible without the use of external resistors. Internal resistors are provided to develop REFT = 2.6 V and REFB = 0.6 V (bias option one) with only two external connections.
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www.ti.com SLAS105D − JANUARY 1995 − REVISED APRIL 2004 PRINCIPLES OF OPERATION TLC5540 18 VDDA 5 V (Analog) R1 320 Ω NOM REFTS 16 17 0.1 µF 2.28 V dc REFT Rref 270 Ω NOM REFB 23 0 V dc 22 REFBS AGND R2 80 Ω NOM 21 Figure 15. External Connections Using the Internal Bias Two Option functional operation Table 2 shows the TLC5540 functions. Table 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC5540CNSR Package Package Pins Type Drawing SO SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) NS 24 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 15.4 2.5 12.0 24.0 Q1 TLC5540INSR SO NS 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 Q1 TLC5540IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5540CNSR SO NS 24 2000 367.0 367.0 45.0 TLC5540INSR SO NS 24 2000 367.0 367.0 45.0 TLC5540IPWR TSSOP PW 24 2000 367.0 367.0 38.
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