Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) PDIP 8

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FEATURES DESCRIPTION

APPLICATIONS

DIN

SCLK

DOUT

OUT

REFIN

AGND

TLC5615C , TLC5615I

SLAS142E – OCTOBER 1996 – REVISED JUNE 2007

10-BIT DIGITAL-TO-ANALOG CONVERTERS

• 10-Bit CMOS Voltage Output DAC in an

The TLC5615 is a 10-bit voltage output

8-Terminal Package

digital-to-analog converter (DAC) with a buffered

reference input (high impedance). The DAC has an

• 5V Single Supply Operation

output voltage range that is two times the reference

• 3-Wire Serial Interface

voltage, and the DAC is monotonic. The device is

• High-Impedance Reference Inputs

simple to use, running from a single supply of 5V. A

power-on-reset function is incorporated to ensure

• Voltage Output Range: 2 Times the Reference

repeatable start-up conditions.

Input Voltage

• Internal Power-On Reset

Digital control of the TLC5615 is over a three-wire

serial bus that is CMOS compatible and easily

• Low Power Consumption: 1.75mW Max

interfaced to industry standard microprocessor and

• Update Rate of 1.21MHz

microcontroller devices. The device receives a 16-bit

• Settling Time to 0.5LSB: 12.5 µ s Typ

data word to produce the analog output. The digital

inputs feature Schmitt triggers for high noise

• Monotonic Over Temperature

immunity. Digital communication protocols include

• Pin-Compatible With the Maxim MAX515

the SPI™, QSPI™, and Microwire™ standards.

The 8-terminal small-outline D package allows digital

control of analog functions in space-critical

• Battery-Powered Test Instruments

applications. The TLC5615C is characterized for

• Digital Offset and Gain Adjustment

operation from 0 ° C to +70 ° C. The TLC5615I is

• Battery Operated/Remote Industrial Controls

characterized for operation from –40 ° C to +85 ° C.

• Machine and Motion Control Devices

D, P, OR DGK PACKAGE

• Cellular Telephones

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 10-BIT DIGITAL-TO-ANALOG CONVERTERS FEATURES • • • • • • • • • • • 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5V Single Supply Operation 3-Wire Serial Interface High-Impedance Reference Inputs Voltage Output Range: 2 Times the Reference Input Voltage Internal Power-On Reset Low Power Consumption: 1.75mW Max Update Rate of 1.21MHz Settling Time to 0.5LSB: 12.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage (VDD to AGND) 7V Digital input voltage range to AGND –0.3V to VDD + 0.3V Reference input voltage range to AGND –0.3V to VDD + 0.3V Output voltage at OUT from external source VDD + 0.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 VOLTAGE OUTPUT (OUT) PARAMETER VO TEST CONDITIONS Voltage output range RL= 10kΩ Output load regulation accuracy VO(OUT) = 2V, IOSC Output short circuit current OUT to VDD or AGND VOL(low) Output voltage, low-level IO(OUT)≤ 5mA VOH(high) Output voltage, high-level IO(OUT)≤– 5mA MIN TYP 0 MAX VDD–0.4 RL = 2kΩ 0.5 20 UNIT V LSB mA 0.25 4.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 OPERATING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 5V ±5%, Vref = 2.048V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.3 0.5 V/µs 12.5 µs ANALOG OUTPUT DYNAMIC PERFORMANCE SR Output slew rate CL = 100pF, TA= +25°C RL = 10kΩ, ts Output settling time To 0.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE 30 20 IO - Output Sink Current - mA 16 VDD = 5 V VREFIN = 2.048 V TA = 25°C IO - Output Source Current - mA 18 14 12 10 8 6 4 VDD = 5 V VREFIN = 2.048 V TA = 25°C 25 20 15 10 5 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 4.8 4.6 5 1.1 1.2 4 3.8 3.6 3.4 Figure 2. Figure 3.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN 70 VDD = 5 V TA = 25°C VREFIN = 4 VPP Signal-To-Noise + Distortion - dB 60 50 40 30 20 10 0 1k 10 k 100 k 300 k Frequency - Hz Figure 6. Differential Nonlinearity – LSB 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0 255 511 767 1023 Integral Nonlinearity – LSB Input Code Figure 7. Differential Nonlinearity With Input Code 1 0.
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TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 APPLICATION INFORMATION GENERAL FUNCTION The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up.
PAGE 9
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 BUFFER AMPLIFIER The output buffer has a rail-to-rail output with short circuit protection and can drive a 2kΩ load with a 100pF load capacitance. Settling time is 12.5µs typical to within 0.5LSB of final value. EXTERNAL REFERENCE The reference voltage input is buffered, which makes the DAC input resistance not code dependent.
PAGE 10
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1).
PAGE 11
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
PAGE 12
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 AC CONSIDERATIONS Digital Feedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.
PAGE 13
TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from D Revision (August 2003) to E Revision ............................................................................................... Page • • Added ESD statement. ..................................................................................................................................................
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) TLC5615IPE4 ACTIVE Package Type Package Pins Package Drawing Qty PDIP P 8 50 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU N / A for Pkg Type (4) -40 to 85 TLC5615IP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC5615CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLC5615CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC5615CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5615CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLC5615CDR SOIC D 8 2500 367.0 367.0 35.0 TLC5615CDR SOIC D 8 2500 340.5 338.1 20.6 TLC5615IDR SOIC D 8 2500 340.5 338.1 20.6 TLC5615IDR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.