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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Zero Reading for 0-V Input

D Precision Null Detection With True Polarity

at Zero

D 1-pA Typical Input Current

D True Differential Input

D Multiplexed Binary-Coded-Decimal (BCD)

Output

D Low Rollover Error: ±1 Count Max

D Control Signals Allow Interfacing With

UARTs or Microprocessors

D Autoranging Capability With Over-and

Under-Range Signals

D TTL-Compatible Outputs

D Second Source to Teledyne TSC7135,

Intersil ICL7135, Maxim ICL7135, and

Siliconix Si7135

D CMOS Technology

DESCRIPTION

The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS

technology. These 4 1/2-digit, dual-slope-integrating, analog-to-digital converters (ADCs) are designed to

provide interfaces to both a microprocessor and a visual display. The digit-drive outputs D1 through D4 and

multiplexed binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD

decoder/drivers as well as microprocessors.

The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of

one count. The zero error is less than 10 µV and zero drift is less than 0.5 µV/°C. Source-impedance errors are

minimized by low input current (less than 10 pA). Rollover error is limited to ±1 count.

The BUSY, STROBE

, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support

microprocessor-based measurement systems. The control signals also can support remote data acquisition

systems with data transfer through universal asynchronous receiver transmitters (UARTs).

The ICL7135C and TLC7135C are characterized for operation from 0°C to 70°C.

AVAILABLE OPTIONS

PACKAGE

PLASTIC DIP

(N)

SMALL OUTLINE

(DW)

0°C to 70°C

ICL7135CN

C to 70

TLC7135CN TLC7135CDW

Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam

during storage or handlilng to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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CC−

REF

ANLG COMMON

INT OUT

AUTO ZERO

BUFF OUT

ref−

ref+

IN−

IN+

CC+

UNDER RANGE

OVER RANGE

STROBE

RUN/HOLD

DGTL GND

POLARITY

CLK

BUSY

DW OR N PACKAGE

(TOP VIEW)

Summary of content (17 pages)

PAGE 1
SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 D Zero Reading for 0-V Input D Precision Null Detection With True Polarity DW OR N PACKAGE (TOP VIEW) at Zero VCC − REF ANLG COMMON INT OUT AUTO ZERO BUFF OUT Cref − Cref + IN − IN + VCC + D5 B1 B2 D 1-pA Typical Input Current D True Differential Input D Multiplexed Binary-Coded-Decimal (BCD) D D D D D D Output Low Rollover Error: ± 1 Count Max Control Signals Allow Interfacing With UARTs o
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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 FUNCTIONAL BLOCK DIAGRAM DIGITAL SECTION POLARITY From Analog Section 23 20 Polarity Flip-Flop Latch 19 18 17 Zero Cross Detect CLK RUN/HOLD OVER RANGE UNDER RANGE STROBE BUSY DGTL GND 22 Latch Control Logic 12 D1 (LSD) D2 D3 Digit Drive Output D4 D5 (MSD) Counters Latch Multiplexer 25 27 28 13 Latch 26 14 21 24 15 16 Latch B1 (LSB) B2 B4 Binary Coded Decimal Output B8 (
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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage (VCC+ with respect to VCC −) 15 V Analog input voltage (IN − or IN +) Reference voltage range VCC − to VCC+ VCC − to VCC+ Clock input voltage range 0 V to VCC+ Operating free-air temperature range, TA 0°C to 70°C Storage temperature range, Tstg −65°C to 150°C Lead temperatur
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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 OPERATING CHARACTERISTICS VCC + = 5 V, VCC − = 5 V, Vref = 1 V, fclock = 120 kHz, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS αFS EL Full-scale temperature coefficient (see Note 1) Linearity error VID = 2 V, 0°C ≤ TA ≤ 70°C −2 V ≤ VID ≤ 2 V ED EFS Differential linearity error (see Note 2) −2 V ≤ VID ≤ 2 V ± Full-scale symmetry error (rollover error) (see Note 3) VID = ±
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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Digital Scan for OVER-RANGE D5 D4 D3 D2 D1 1000 Counts Figure 2 Integrator Output AUTO ZERO 10,001 Counts Signal Int 10,000 Counts De-Integrate 20,001 Counts Max Full Measurement Cycle 40,002 Counts BUSY OVER RANGE When Applicable UNDER RANGE When Applicable Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 STROBE AUTO ZERO Digit Scan for OVER RANGE Signal Integrate Deintegrate† D5† D4 D3 D2 D1 † First D5 of AUTO ZERO and deintegrate is one count longer. Figure 4 PRINCIPLES OF OPERATION A measurement cycle for the ICL7135C and TLC7135C consists of the following four phases. 1. Auto-Zero Phase.
PAGE 7
SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 DESCRIPTION OF ANALOG CIRCUITS Input Signal Range The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential and common-mode voltages cause the integrator output to swing.
PAGE 8
SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 BUSY Output The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first clock pulse after zero crossing or at the end of the measurement cycle when an over-range condition occurs. It is possible to use the BUSY terminal to serially transmit the conversion result.
PAGE 9
SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Integrating Capacitor The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing without causing the integrating amplifier output to saturate and get too close to the power supply voltages. When the amplifier output is within 0.3 V of either supply, saturation occurs.
PAGE 10
SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003 Minimum Clock Frequency The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference capacitors. Measurement cycles as high as 10 µs are not influenced by leakage error.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC7135CDWR Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7135CDWR SOIC DW 28 1000 367.0 367.0 55.
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MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.
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