Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) PDIP 16

  

   

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Easily Interfaced to Microprocessors

D On-Chip Data Latches

D Monotonic Over the Entire A/D Conversion

Range

D Segmented High-Order Bits Ensure

Low-Glitch Output

D Interchangeable With Analog Devices

AD7524, PMI PM-7524, and Micro Power

Systems MP7524

D Fast Control Signaling for Digital

Signal-Processor Applications Including

Interface With TMS320

D CMOS Technology

KEY PERFORMANCE SPECIFICATIONS

Resolution

Linearity error

Power dissipation at V

= 5V

Setting time

Propagation delay time

8 Bits

1/2LSB Max

5mW Max

100ns Max

80ns Max

description

The TLC7524C, TLC7524E, and TLC7524I are

CMOS, 8-bit, digital-to-analog converters (DACs)

designed for easy interface to most popular

microprocessors.

The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random

access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,

which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film

resistors or laser trimming, while dissipating less than 5mW typically.

Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses

or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many

microprocessor-controlled gain-setting and signal-control applications.

The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation

from −25°C to +85°C. The TLC7524E is characterized for operation from −40°C to +85°C.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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OUT1

OUT2

GND

DB7

DB6

DB5

DB4

DB3

REF

DB0

DB1

DB2

3212019

910111213

DB0

GND

DB7

DB6

DB5

FN PACKAGE

(TOP VIEW)

OUT2

OUT1

DB2

DB1

REF

DB4

DB3

NC−No internal connection

D, N, OR PW PACKAGE

(TOP VIEW)

Summary of content (21 pages)

PAGE 1
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 D Easily Interfaced to Microprocessors D On-Chip Data Latches D Monotonic Over the Entire A/D Conversion D D D OUT1 OUT2 GND DB7 DB6 DB5 DB4 DB3 Range Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524 Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320 CMOS
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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 functional block diagram REF R 15 2R R 2R R 2R 2R 2R 16 S-1 S-2 S-3 S-8 R 1 2 CS WR 12 3 Data Latches 13 4 DB7 (MSB) 5 DB6 6 DB5 RFB OUT1 OUT2 GND 11 DB0 (LSB) Data Inputs Terminal numbers shown are for the D or N package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . .
PAGE 3
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 recommended operating conditions Supply voltage, VDD VDD = 5V MIN NOM MAX VDD = 15V MIN NOM MAX 4.75 14.5 5 5.25 ± 10 Reference voltage, Vref High-level input voltage, VIH 15 2.4 V 0.8 40 CS hold time, th(CS) V V 13.5 Low-level input voltage, VIL CS setup time, tsu(CS) 15.5 ± 10 UNIT 1.
PAGE 4
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 operating characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V MIN TYP MAX VDD = 15V TYP MIN MAX UNIT ± 0.5 ± 0.5 LSB Linearity error Gain error See Note 1 ± 2.5 ± 2.
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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage mode.
PAGE 6
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder, analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded.
PAGE 7
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION VDD Vref RA = 2 kΩ (see Note A) RB C (see Note B) RFB DB0−DB7 OUT1 − OUT2 + Output CS WR GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3.
PAGE 8
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces D0−D7 Data Bus Z−80A DB0−DB7 WR TLC7524 WR OUT1 OUT2 CS IORQ Decode Logic Address Bus A0−A15 Figure 5. TLC7524: Z-80A Interface Data Bus D0−D7 6800 DB0−DB7 φ2 WR TLC7524 OUT1 OUT2 CS VMA A0−A15 Decode Logic Address Bus Figure 6.
PAGE 9
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces (continued) A8−A15 Address Bus 8051 Decode Logic 8-Bit Latch CS WR ALE TLC7524 DB0−DB7 OUT1 OUT2 WR AD0−AD7 Adress/Data Bus Figure 7.
PAGE 10
Revision History DATE REV 6/07 D PAGE SECTION DESCRIPTION Front Page — Deleted Available Options table. 2 — Inserted Package/Ordering information. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC7524CDR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLC7524CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TLC7524CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7524CDR SOIC D 16 2500 367.0 367.0 38.0 TLC7524CNSR SO NS 16 2000 367.0 367.0 38.0 TLC7524CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLC7524EDR SOIC D 16 2500 367.0 367.0 38.0 TLC7524IDR SOIC D 16 2500 367.0 367.0 38.0 TLC7524IPWR TSSOP PW 16 2000 367.0 367.0 35.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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