Datasheet

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  

  

 

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Easily Interfaced to Microprocessors

D On-Chip Data Latches

D Monotonic Over the Entire A/D Conversion

Range

D Interchangeable With Analog Devices

AD7528 and PMI PM-7528

D Fast Control Signaling for Digital Signal

Processor (DSP) Applications Including

Interface With TMS320

D Voltage-Mode Operation

D CMOS Technology

KEY PERFORMANCE SPECIFICATIONS

Resolution

Linearity Error

Power Dissipation at V

= 5V

Settling Time at V

= 5V

Propagation Delay Time at V

= 5V

8 bits

1/2LSB

20mW

100ns

80ns

description

The TLC7528C, TLC7528E, and TLC7528I are

dual, 8-bit, digital-to-analog converters (DACs)

designed with separate on-chip data latches and

feature exceptionally close DAC-to-DAC match-

ing. Data are transferred to either of the two DAC

data latches through a common, 8-bit, input port.

Control input DACA

/DACB determines which

DAC is to be loaded. The load cycle of these

devices is similar to the write cycle of a

random-access memory, allowing easy interface

to most popular microprocessor buses and output

ports. Segmenting the high-order bits minimizes

glitches during changes in the most significant

bits, where glitch impulse is typically the

strongest.

These devices operate from a 5V to 15V power supply and dissipates less than 15mW (typical). The 2- or

4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting

and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than

a current output. Refer to the typical application information in this data sheet.

The TLC7528C is characterized for operation from 0°C to +70°C. The TLC7528I is characterized for operation

from −25°C to +85°C. The TLC7528E is characterized for operation from −40°C to +85°C.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

AGND

OUTA

RFBA

REFA

DGND

DACA

/DACB

(MSB) DB7

DB6

DB5

DB4

OUTB

RFBB

REFB

DB0 (LSB)

DB1

DB2

DB3

DW, N OR PW PACKAGE

(TOP VIEW)

3212019

910111213

REFB

DB0 (LSB)

REFA

DGND

DACA/DACB

(MSB) DB7

DB6

FN PACKAGE

(TOP VIEW)

RFBA

OUTA

AGND

OUTB

RFBB

Summary of content (27 pages)

PAGE 1
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 D Easily Interfaced to Microprocessors D On-Chip Data Latches D Monotonic Over the Entire A/D Conversion D D D D Range Interchangeable With Analog Devices AD7528 and PMI PM-7528 Fast Control Signaling for Digital Signal Processor (DSP) Applications Including Interface With TMS320 Voltage-Mode Operation CMOS Technology DW, N OR PW PACKAGE (TOP VIEW) AGND OUTA RFBA REFA DGND DACA/DAC
PAGE 2
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 functional block diagram DB0 14 REFA 13 12 8 11 Data Inputs Input Buffer 10 Latch A 9 8 DB7 DACA/DACB WR CS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ RFBA 4 8 2 OUTA DACA 1 AGND 7 8 6 16 Logic Control 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Latch B 8 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ DACB 18 REFB operating sequence tsu(CS) th(CS) tsu(DAC) th(DAC) CS DACA/DACB tw(WR) WR tsu(D) Data I
PAGE 3
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 electrical characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10V, VOA and VOB at 0V (unless otherwise noted) PARAMETER IIH IIL TEST CONDITIONS High-level input current VI = VDD VI = 0 Low-level input current VDD = 5V MIN TYP† MAX VDD = 15V MIN TYP† MAX 10 10 µA −10 µA 20 20 kΩ 5 Reference input impedance REFA or REFB to AGND IIkg
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 operating characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10V, VOA and VOB at 0V (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V MIN TYP MAX VDD = 15V MIN TYP MAX UNIT ± 1/2 ± 1/2 LSB Linearity error Settling time (to 1/2LSB) See Note 1 100 100 ns Gain error See Note 2 2.5 2.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 PRINCIPLES OF OPERATION The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5V. These devices can operate with any supply voltage in the range from 5V to 15V; however, input logic levels are not TTL-compatible above 5V. R R R REFA 2R 2R 2R 2R 2R RFB S1 S2 S3 RFBA S8 OUTA AGND DACA Data Latches and Drivers Figure 1.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant and 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input coding for unipolar and bipolar operation, respectively.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION VI(A) ± 10 V R6 20 kΩ (see Note B) R1 (see Note A) DACA/ DACB 15 CS 16 WR 5 OUTA 8 DACA 8 ÎÎÎ ÎÎÎ Latch A1 AGND RFBB Control Logic DGND Latch OUTB DACB REFB AGND R8 20 kΩ A3 AGND VOA R11 5 kΩ R4 (see Note A) C2 (see Note C) 8 − A2 + (see Note B) + 6 ÎÎÎ ÎÎÎ R9 10 kΩ (see Note B) R3 (see Note A) A4 + 7 8 − Input Buffer R5 20 k
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION microprocessor interface information 8 Address Bus A8 −A15 DACA/DACB Address Decode Logic CPU 8051 A CS A+1 WR TLC7528 DB0 WR DB7 ALE Latch 8 Data Bus AD0 −AD7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 5.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION 8 Address Bus A8 −A15 DACA/DACB Address Decode Logic IORQ A CS TLC7528 WR A+1 CPU Z80-A DB0 DB7 WR 8 Data Bus D0 −D7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 7.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION VCC VDD Test Input 0 to −Vref 3 17 RFBA 1 kΩ OUTA − 4 2 DACA REFA + 8 14 −7 Data Inputs DB0 −DB7 TLC7528 15 16 6 CS 1 WR DACA / DACB OUTB DACB + 5 20 − 18 REFB Vref PASS / FAIL Output AGND DGND RFBB 19 Figure 8.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION Table 3. Attenuation vs DACA, DACB Code ATTEN (dB) DAC INPUT CODE CODE IN DECIMAL ATTN (dB) DAC INPUT CODE CODE IN DECIMAL 0 11111111 255 8.0 01100110 102 0.5 11110010 242 8.5 01100000 96 1.0 11100100 228 9.0 01011011 91 1.5 11010111 215 9.5 01010110 86 2.0 11001011 203 10.0 01010001 81 2.5 11000000 192 10.
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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION C3 47 pF 17 Data In REFA DACA (RS) VDD RFBA 8 AGND TLC7528 15 16 5 6 3 30 kΩ R4 A1 1 30 kΩ R3 CS OUTB DACB (RF) WR R5 RFBB DGND 20 A2 10 kΩ + VI OUTA 2 + 4 19 High Pass Out REFB 18 DACA / DACB Bandpass Out DACA1 AND DACB1 C1 1000 pF Data In OUTA 2 DACA (R1) VDD RFBA 8 TLC7528 15 16 5 6 AGND 1 C2 OUTB 20 1000 pF CS DACB
PAGE 14
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008 APPLICATION INFORMATION voltage-mode operation It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal.
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Revision History DATE REV PAGE SECTION DESCRIPTION 11/08 E 13 Application Information Front Page — Deleted Available Options table. 6/07 D 3 — Inserted Package/Ordering information. Corrected Figure 10. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Jan-2013 Status (1) TLC7528IPWRG4 ACTIVE Package Type Package Pins Package Qty Drawing TSSOP PW 20 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -25 to 85 TLC7528I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC7528CNSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 TLC7528EDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLC7528IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7528CNSR SO NS 20 2000 367.0 367.0 45.0 TLC7528EDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC7528IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC7528IPWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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