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ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage reference Virtual ground Adjustable TO 92 3

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  

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SLOS098D − AUGUST 1991 − REVISED MAY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 1/2 V

Virtual Ground for Analog Systems

D Self-Contained 3-terminal TO-226AA

Package

D Micropower Operation . . . 170 µA Typ,

= 5 V

D Wide V

Range ...4 V to 40 V

D High Output-Current Capability

− Source . . . 20 mA Typ

− Sink . . . 20 mA Typ

D Excellent Output Regulation

− −45 µV Typ at I

= 0 to −10 mA

− +15 µV Typ at I

= 0 to +10 mA

D Low-Impedance Output . . . 0.0075 Ω Typ

D Noise Reduction Pin (D, JG, and P

Packages Only)

description

In signal-conditioning applications utilizing a

single power source, a reference voltage equal to

one-half the supply voltage is required for

termination of all analog signal grounds. Texas

Instruments presents a precision virtual ground

whose output voltage is always equal to one-half

the input voltage, the TLE2426 “rail splitter.”

The unique combination of a high-performance,

micropower operational amplifier and a precision-

trimmed divider on a single silicon chip results in

a precise V

ratio of 0.5 while sinking and

sourcing current. The TLE2426 provides a low-

impedance output with 20 mA of sink and source

capability while drawing less than 280 µA

of supply current over the full input range of 4 V to 40 V. A designer need not pay the price in terms of board

space for a conventional signal ground consisting of resistors, capacitors, operational amplifiers, and voltage

references. The performance and precision of the TLE2426 is available in an easy-to-use, space saving,

3-terminal LP package. For increased performance, the optional 8-pin packages provide a noise-reduction pin.

With the addition of an external capacitor (C

), peak-to-peak noise is reduced while line ripple rejection is

improved.

Initial output tolerance for a single 5-V or 12-V system is better than 1% with 3.6% over the full 40-V input range.

Ripple rejection exceeds 12 bits of accuracy. Whether the application is for a data acquisition front end, analog

signal termination, or simply a precision voltage reference, the TLE2426 eliminates a major source of system

error.

AVAILABLE OPTIONS

PACKAGED DEVICES

CHIP

SMALL

OUTLINE

(D)

CERAMIC

DIP

(JG)

PLASTIC

(LP)

PLASTIC

DIP

(P)

CHIP

FORM

(Y)

0°C to 70°C TLE2426CD — TLE2426CLP TLE2426CP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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0 0.25 0.5 0.75 1

Voltage − V

t − Time − s

INPUT/OUTPUT TRANSFER CHARACTERISTICS

Summary of content (30 pages)

PAGE 1
SLOS098D − AUGUST 1991 − REVISED MAY 1998 D 1/2 VI Virtual Ground for Analog Systems D Self-Contained 3-terminal TO-226AA D Excellent Output Regulation Package D D D Micropower Operation . . . 170 µA Typ, D D VI = 5 V Wide VI Range . . . 4 V to 40 V High Output-Current Capability − Source . . . 20 mA Typ − Sink . . . 20 mA Typ − −45 µV Typ at IO = 0 to −10 mA − +15 µV Typ at IO = 0 to + 10 mA Low-Impedance Output . . . 0.
PAGE 2
SLOS098D − AUGUST 1991 − REVISED MAY 1998 −40°C to 85°C TLE2426ID −55°C to 125°C TLE2426MD — TLE2426ILP TLE2426IP TLE2426MJG TLE2426MLP TLE2426MP TLE2426Y The D and LP packages are available taped and reeled in the commercial temperature range only. Add R suffix to the device type (e. g., TLC2426CDR). Chips are tested at 25°C.
PAGE 3
SLOS098D − AUGUST 1991 − REVISED MAY 1998 description (continued) The C-suffix devices are characterized for operation from 0°C to 70°C. The I suffix devices are characterized for operation from −40°C to 85°C. The M suffix devices are characterized over the full military temperature range of −55°C to 125°C.
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SLOS098D − AUGUST 1991 − REVISED MAY 1998 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Continuous input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Continuous filter trap voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 5 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 5 V TA† 25°C 25 C VI = 40 V VI = 5 V Full range Temperature coefficient of output voltage VI = 5 V VI = 4 to 40 V TLE2426C MIN TYP MAX 1.98 2 2.02 2.48 2.5 2.52 19.8 20 20.2 2.
PAGE 6
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 12 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 12 V TA† 25°C 25 C VI = 40 V VI = 12 V Full range Temperature coefficient of output voltage VI = 12 V VI = 4 to 40 V TLE2426C MIN TYP MAX 1.98 2 2.02 5.95 6 6.05 19.8 20 20.2 5.
PAGE 7
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 5 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 5 V TA† 25°C 25 C VI = 40 V VI = 5 V Full range Temperature coefficient of output voltage VI = 5 V VI = 4 to 40 V Supply current No load Output voltage regulation (sourcing current)‡ IO = 0 to − 10 mA TYP MAX 1.98 2 2.02 2.48 2.
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SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 12 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 12 V TA† 25°C 25 C VI = 40 V VI = 12 V Full range Temperature coefficient of output voltage VI = 12 V VI = 4 to 40 V Supply current No load Output voltage regulation (sourcing current)‡ IO = 0 to − 10 mA Output voltage regulation (sink
PAGE 9
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 5 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 5 V TA† 25°C 25 C VI = 40 V VI = 5 V Full range Temperature coefficient of output voltage VI = 5 V VI = 4 to 40 V Supply current No load Output voltage regulation (sourcing current)‡ IO = 0 to − 10 mA Output voltage regulation (sinking
PAGE 10
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 12 V, IO = 0 (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS VI = 4 V VI = 12 V TA† 25°C 25 C VI = 40 V VI = 12 V Full range Temperature coefficient of output voltage VI = 12 V VI = 4 to 40 V Supply current No load Output voltage regulation (sourcing current)‡ IO = 0 to − 10 mA Output voltage regulation (sink
PAGE 11
SLOS098D − AUGUST 1991 − REVISED MAY 1998 electrical characteristics at specified free-air temperature, VI = 5 V, IO = 0, TA = 25°C (unless otherwise noted) PARAMETER Output voltage TEST CONDITIONS TLE2426Y MIN VI = 5 V No load Supply current Output voltage regulation (sourcing current)† IO = 0 to − 10 mA IO = 0 to − 20 mA Output voltage regulation (sinking current)† IO = 0 to 10 mA IO = 0 to 20 mA TYP MAX UNIT 2.
PAGE 12
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS Table Of Graphs FIGURE Output voltage Distribution Output voltage change vs Free-air temperature 3 Output voltage error vs Input voltage 4 vs Input voltage 5 Input bias current vs Free-air temperature 6 Output voltage regulation vs Output current 7 Output impedance vs Frequency 8 Short-circuit output current 12 1,2 vs Input voltage 9,10 vs Free-air temperat
PAGE 13
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS† DISTRIBUTION OF OUTPUT VOLTAGE DISTRIBUTION OF OUTPUT VOLTAGE 3 Percentage of Units − % Percentage of Units − % 2.5 40 98 Units Tested From 2 Wafer Lots VI = 5 V TA = 25°C 2 1.5 1 98 Units Tested From 2 Wafer Lots VI = 12 V TA = 25°C 30 20 10 0.5 0 2.48 0 2.49 2.5 2.51 VO − Output Voltage − V 2.52 6.05 6.075 6.
PAGE 14
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS† INPUT BIAS CURRENT vs INPUT VOLTAGE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 300 300 IO = 0 VI = 40 V 250 TA = 25°C IIB I IB − Input Bias Current − µ A IIB I IB − Input Bias Current − µ A 250 200 TA = − 55°C 150 TA = 125°C 100 VI = 12 V 200 VI = 5 V 150 VI = 4 V 100 50 50 IO = 0 0 0 0 5 10 15 20 25 30 35 40 −75 −50 VI − Input Voltage − V 125 Figure
PAGE 15
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS† SHORT-CIRCUIT OUTPUT CURRENT vs INPUT VOLTAGE SHORT-CIRCUIT OUTPUT CURRENT vs INPUT VOLTAGE 40 VO = GND (Output Sourcing) IOS I OS − Short-Circuit Output Current − mA IOS I OS − Short-Circuit Output Current − mA 0 −20 −40 TA = − 55°C −60 TA = 125°C TA = 25°C TA = 25°C TA = − 55°C 30 TA = 125°C 20 10 VO = VI (Output Sinking) 0 −80 0 5 10 15 20 30 25 35 0 40 5
PAGE 16
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS RIPPLE REJECTION vs FREQUENCY SPECTRAL NOISE VOLTAGE DENSITY vs FREQUENCY 400 VI = 5 V or 12 V ∆VI(PP) = 1 V IO = 0 TA = 25°C 90 Ripple Rejection − dB 80 Vn − Spectral Noise Voltage Density − nV/ Hz 100 CNR = 1 µF 70 60 50 40 30 20 CNR = 0 10 VI = 5 V or 12 V TA = 25°C 300 200 100 CNR = 0 CNR = 1 µF 0 0 10 100 1k 10 k 100 k 10 1 1M 100 1k f − Frequency − Hz
PAGE 17
SLOS098D − AUGUST 1991 − REVISED MAY 1998 TYPICAL CHARACTERISTICS STABILITY RANGE OUTPUT CURRENT vs LOAD CAPACITANCE 20 15 VI = 5 V TA = 25°C Unstable I O − Output Current − mA 10 5 0 Stable −5 −10 −15 −20 10 −6 10 −5 10 −4 10 −3 10 −2 10 −1 10 0 CL− Load Capacitance − mF 10 1 10 2 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17
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SLOS098D − AUGUST 1991 − REVISED MAY 1998 MACROMODEL INFORMATION * * * * TLE2426 OPERATIONAL AMPLIFIER “MACROMODEL” SUBCIRCUIT CREATED USING PARTS RELEASE 4.03 0N 08/21/90 AT 13:51 REV (N/A) SUPPLY VOLTAGE: 5 V CONNECTIONS: FILTER | INPUT * | | COMMON * | | | OUTPUT * | | | | .
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLE2426CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2426IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLE2426CDR SOIC D 8 2500 367.0 367.0 35.0 TLE2426IDR SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.