TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Check for Samples: TLK100 1 Introduction 1.1 Features 1 • • • • • • • • • • • • Temperature From –40°C to 85°C Low Power Consumption, < 200mW Typical Cable Diagnostics Error-Free Operation up to 200 Meters Under Typical Conditions 3.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com RX_CLK RXD[3:0] RX_DV RX_ER COL MDC MDIO TX_EN TX_CLK TXD[3:0] Serial Management CRS/CRS_DV MII MII Interface TX_DATA RX_CLK TX_CLK RX_DATA MII Registers 10BASE-T and 100BASE-TX 10BASE-T and 100BASE-TX Auto-Negotiation State Machine Transmit Block Receive Block Clock Generation DAC ADC BIST Boundary Scan JTAG TD± LED Drivers Cable Diagnostics Auto-MDIX RD± LEDs Reference Clock B0313-01 Figure 1-1.
TLK100 www.ti.com 1.5 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Pin Layout LED_LINK / AN_0 LED_SPEED / AN_1 LED_ACT / AN_EN MDIO MDC MII_RX_ERR / MDIX_EN MII_RX_DV VDD33_IO MII_RXD_3 / PHYAD4 MII_RXD_2 / PHYAD3 MII_RXD_1 / PHYAD2 MII_RXD_0 / PHYAD1 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 Figure 1-2.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 1 2 3 4 5 4 www.ti.com .............................................. 1 1.1 Features .............................................. 1 1.2 Applications .......................................... 1 1.3 General Description .................................. 1 1.4 System Diagram ..................................... 1 1.5 Pin Layout ............................................ 3 Pin Descriptions ......................................... 5 2.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 2 Pin Descriptions The TLK100 pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Configuration (Jumper) Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground pins Note: Configuration pin option. See Section 2.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 2.2 www.ti.com MAC Data Interface PIN NAME NO. TYPE DESCRIPTION MII_TX_CLK 19 O, PD MII TRANSMIT CLOCK: : MII Transmit Clock provides 25MHz or 2.5MHz reference clock depending on the speed. MII_TX_EN 18 I, PD MII TRANSMIT ENABLE: MII_TX_EN is presented on the rising edge of the MII_TX_CLK . It indicates the presence of valid data inputs on MII_TXD[3:0]. It is an active high signal.
TLK100 www.ti.com 2.5 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 JTAG Interface PIN NAME NO. TYPE DESCRIPTION JTAG_TCK 44 I, PU This pin is the test clock.This pin has a weak internal pullup. JTAG_TDI 45 I, PU This pin is the test data input.This pin has a weak internal pullup. JTAG_TDO 47 O JTAG_TMS 46 I, PU JTAG_TRST N 48 I, PU 2.6 This pin is the test data output. This pin selects the test mode. This pin has a weak internal pullup.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 2.7 www.ti.com Jumper Options Jumper option is an elegant way to configure the TLK100 into specific modes of operation. Some of the functional pins are used as jumper options. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. Below table shows the pins used for the jumper option and its description. The functional pin name is indicated in parentheses. A 2.
TLK100 www.ti.com 2.8 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 10 Mb/s and 100 Mb/s PMD Interface PIN NAME TYPE NO. DESCRIPTION Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. TD–, TD+ 8, 9 I/O In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 1.8V or 3.3V bias for operation. Differential receive input (PMD Input Pair).
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 2.10 Power Supply Configuration The TLK100 provides best-in-class flexibility of power supplies. • Single supply operation – If a single 3.3V power supply is desired, the TLK100 will sense the presence of the supply and configure the internal voltage regulators to provide all necessary supply voltages. To operate in this mode, connect the TLK100 supply pins according to the following scheme: 3.3V Supply 3.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 1.8V Supply 1.8V Supply Pin 41 (VDD33_V18) Pin 5 (RD–) Pin 40 (V18_PFBOUT) 49.9W Pin 2 (V18_PFBIN) 49.9W 1.8V Supply 1:1 0.1mF Pin 6 (RD+) Pin 4 (V18_PFBIN2) RD– RD+ 0.1mF* TLK100 Pin 8 (TD–) TD– 1.8V Supply 49.9W TD+ 0.1mF* 0.1mF 49.9W 1:1 T1 RJ45 Pin 9 (TD+) Figure 2-2. Power Scheme for Operation With External 1.8V Supply – External 1.1V rail – When external 1.1V rail is available – Connect the external 1.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Other power supply options – Because the TLK100 incorporates independent voltage regulators, designers may take advantage of several optional configurations, depending on available power supplies. See Table 2-1 for these options. Table 2-1. Power Supply Options MAC I/F (3.3V) Transformer CT (3.3V or 1.8V) Voltage Source Voltage Source Regulator (ON/OFF) Voltage Source Regulators (ON/OFF) Voltage Source 3.3V from external supply 3.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 3 Configuration This section includes information on the various configuration options available with the TLK100. The configuration options described below include: • Auto-Negotiation • Auto-MDIX • PHY Address • LED Interface • Loopback Functionality • BIST • Cable Diagnostics 3.1 Auto-Negotiation The TLK100 device can auto-negotiate to operate in 10BASE-T or 100BASE-TX.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com The Auto-Negotiation function can also be controlled by internal register access using registers as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u specification. 3.2 Auto-MDIX The TLK100 device automatically determines whether or not it needs to cross over between pairs so that an external crossover cable is not required.
TLK100 www.ti.com 3.3 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 PHY Address The 5 PHY address inputs pins are shared with the MII_RXD[3:0] pins and COL pin as shown in Table 3-2. Table 3-2. PHY Address Mapping PIN # PHYAD FUNCTION RXD FUNCTION 24 PHYAD0 MII_COL 25 PHYAD1 MII_RXD_0 26 PHYAD2 MII_RXD_1 27 PHYAD3 MII_RXD_2 28 PHYAD4 MII_RXD_3 Each TLK100 or port sharing an MDIO bus in a system must have a unique physical address.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 3.4 www.ti.com LED Interface The TLK100 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes. The LEDs can be controlled by configuration pin and/or internal register bits. Bits 6:5 of the LED Direct Control register (LEDCR) selects the LED mode as described in Table 3-3. Table 3-3.
TLK100 www.ti.com 3.5 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Loopback Functionality The TLK100 provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK100 digital and analog data path. Generally, the TLK100 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. 3.5.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 3.5.2 www.ti.com Far-End Loopback Far-end (Reverse) loopback is a special test mode to allow testing the PHY from link partner side. In this mode data that is received from the link partner pass through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-4 shows Far-end loopback functionality.
TLK100 www.ti.com 3.7 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Cable Diagnostics With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results with the need to non-intrusively identify and report cable faults. TI cable diagnostic unit provides extensive information about cable integrity.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 3.7.2 www.ti.com ALCD The TLK100 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. It uses passive digital signal processing based on adapted data thus enabling measurement of cable length with an active link partner. The ALCD also uses pre-defined parameters according to the cable properties (e.g.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 4 Interfaces 4.1 Media Independent Interface (MII) The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 4.2 www.ti.com Serial Management Interface The Serial Management Interface (SMI), provides access to the TLK100’s internal registers space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002 in addition to several others, providing additional visibility and controllability of the TLK100 device.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 For write transactions, the station-management entity writes data to the addressed TLK100, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-3 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 4-1, Figure 4-2, and Figure 4-3. Table 4-1.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 • • • • www.ti.com ADDAR is the address/data MMD register. It is used in conjunction with REGCR to provide the access to the extended register set. If register REGCR[15:14] is 00, then ADDAR holds the address of the extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended register set address register.
TLK100 www.ti.com 4.2.1.3 To 1. 2. 3. 4. SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Write (no post increment) Operation write an extended register set register: Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. Write the desired register address to register ADDAR. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR. Write the content of the desired extended register set register to register ADDAR.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 5 Architecture The TLK100 Fast Ethernet transceiver is physical layer core for Ethernet 100Base-TX and 10Base-T applications. It contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII) for direct connection to a MAC/Switch port.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data stream until the next transmit packet is detected. Table 5-1.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 5.1.3 www.ti.com NRZI and MLT-3 Encoding To comply with the TP-PMD standard for 100BASE-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'. 5.1.
TLK100 www.ti.com 5.2.4 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 NRZI and MMLT-3 Decoding The TLK100 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler. 5.2.5 Descrambler The descrambler is used to descramble the received NRZ data. It is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 5.2.10 Signal Detect The signal detect function of the TLK100 is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters. The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability.
TLK100 www.ti.com 5.3.3 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Jabber Function Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK100 output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com determine if and how to cross. In some of the configurations, there may be situations in which the link is not established. Particularly, it may occur if the TLK100 is forced to operate in 10B-T or 100B-TX modes (auto-negotiation is disabled) and the other link partner activates auto-negotiation. For that reason, it is recommended to disable the auto MDI/MDI-X function prior to disabling the auto-negotiation.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK100 operation. For the changes to take place, issue a restart command through register BMCR (0x0000h) bit 9. 5.5.3 Configuration Bits The auto-negotiation options can be configured through the configuration bits AN_EN, AN_1 and AN_0 as described in Table 5-3.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 6 Reset and Power Down Operation At power up it is recommended to have the external reset pin (RESETN) active (low). The RESETN pin should be de-asserted 200μs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to be stabilized. If required during normal operation, the device can be reset by a hardware or software reset. 6.
TLK100 www.ti.com 6.4 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Power Down Modes TLK100 supports four types of power saving modes. The lowest power consumption is in the "Extreme Low Power" mode (ELP). To enter into the ELP mode the PWRDNN/INT pin is pulled LOW. To enable the power-down modes described below, set bit 11 of register BMCR (0x00h) to '1'.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 7 Design Guidelines 7.1 TPI Network Circuit Figure 7-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.
TLK100 www.ti.com 7.2.2 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Crystal The use of a 25MHz, parallel, 20pF-load crystal resonator is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 7.3 www.ti.com Thermal Vias Recommendation The following thermal via guidelines apply to GNDPAD, pin 49: 1. Thermal via size = 0.2 mm 2. Recommend 4 vias 3. Vias have a center to center separation of 2 mm. Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 7-3 illustrates an example layout. M0117-01 Figure 7-3.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8 Register Block Table 8-1.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 40 www.ti.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 8-2.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 8-2.
TLK100 www.ti.com 8.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.1.1 www.ti.com Basic Mode Control Register (BMCR) Table 8-3. Basic Mode Control Register (BMCR), address 0x0000 BIT 15 BIT NAME Reset DEFAULT 0, RW/SC DESCRIPTION PHY Software Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. Writing a 1 to this bit causes the PHY to be reset. When the reset operation is done, this bit is cleared to 0 automatically. The configuration is relatched.
TLK100 www.ti.com 8.1.2 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Basic Mode Status Register (BMSR) Table 8-4. Basic Mode Status Register (BMSR), address 0x0001 BIT BIT NAME DEFAULT 15 100BASE-T4 0, RO/P 14 100BASE-TX Full Duplex 1, RO/P 100BASE-TX Half Duplex 1, RO/P 10BASE-T Full Duplex 1, RO/P 10BASE-T Half Duplex 1, RO/P DESCRIPTION 100BASE-T4 Capable: This protocol is not available. Always 0 = Device does not perform 100BASE-T4 mode.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.1.3 www.ti.com PHY Identifier Register #1 (PHYIDR1) Table 8-5. PHY Identifier Register #1 (PHYIDR1), address 0x0002 BIT 15 8.1.4 BIT NAME OUI_MSB DEFAULT DESCRIPTION <0010 0000 0000 0000>, RO/P OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h) are stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2).
TLK100 www.ti.com 8.1.5 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto- Negotiation. Table 8-7. Auto Negotiation Advertisement Register (ANAR), address 0x0004 BIT 15 BIT NAME NP DEFAULT 0, RW DESCRIPTION Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.1.6 www.ti.com Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 8-8.
TLK100 www.ti.com 8.1.7 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 8-9. Auto-Negotiate Expansion Register (ANER), address 0x0006 BIT BIT NAME 15:5 RESERVED 4 PDF DEFAULT DESCRIPTION 0, RO RESERVED: Writes ignored, Read as 0. 0, RO Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.1.8 www.ti.com Auto-Negotiate Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 8-10. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x0007 BIT BIT NAME 15 NP DEFAULT 0, RW DESCRIPTION Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired.
TLK100 www.ti.com 8.1.9 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 8-11. Auto-Negotiation Link Partner Ability Register Next Page (ANLNPTR), address 0x0008 BIT 15 BIT NAME NP DEFAULT 0, RO DESCRIPTION Next Page Indication: 1 = No other Next Page Transfer desired.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.2 www.ti.com Register Control Register (REGCR) This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. It also contains selection bits for auto increment of the data register. Table 8-12. Register Control Register (REGCR), address 0x000D BIT BIT NAME DEFAULT DESCRIPTION 15:1 Function 4 0, RW 00 01 10 11 13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK100 www.ti.com 8.4 8.4.1 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Extended Registers PHY Control Register (PHYCR) This register provides quick access to commonly accessed PHY control information. Table 8-14.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.4.2 www.ti.com PHY Status Register (PHYSR) This register implements the PHY Specific Status register. Table 8-15.
TLK100 www.ti.com 8.4.3 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 MII Interrupt Mask Register (MINTMR) This register contains enables for various interrupt functions supported by TLK100. Table 8-16.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.4.4 www.ti.com MII Interrupt Status Register (MINTSR) This register gives the status of the different interrupt function supported by TLK100. Table 8-17.
TLK100 www.ti.com 8.4.6 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Receiver Error Counter Register (RECR) This counter keeps count of the number of receive errors. Table 8-19. Receiver Error Counter Register (RECR), address 0x0015 BIT 15:0 8.4.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.4.9 www.ti.com BIST Byte Count Register (BISBCR) This register gives the total number of bytes received by the PRBS checker. Table 8-22. BIST Count Register (BISBCR), address 0x0071 BIT BIT NAME 15:0 prbs_byte_cnt DEFAULT 0, RO DESCRIPTION Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register 0x0072 bit[0] or bit[1].
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.4.13 LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. The polarity, pulse width and blink rates can be programmed using this register. Table 8-26.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 8.4.15 False Carrier Sense Counter Register (FCSCR) This register counts the error nibbles between the IDLE nibbles (BAD_SSD), in nibble time. This count register is reset when this register is read. Table 8-28. False Carrier Sense Counter Register (FCSCR), address 0x0042 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0, RO Ignore on read 7:0 0, RO IDLE error counter value.
TLK100 www.ti.com 8.5.2 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Cable Diagnostic Status Register (CDSR) This register gives the status of the cable diagnostic tests. It also allows configuring different modes of the ALCD and DSA tests. Table 8-31.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.5.5 www.ti.com TDR Pattern Amplitude Register (TDRPAR) This register allows to program the pattern used to generate the TDR pulses. Bits 4:0 of this register give the amplitude of the TDR pulse. A value of 0x8 maps to an amplitude of 1V. For values from 0x8 to 0xF the amplitude is saturated to 1V. The TDR pattern is 16 symbols long. So, sixteen consecutive writes to this register are required.
TLK100 www.ti.com 8.5.8 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 TDR Control Register (TDRCR) This register allows configuring the TDR modes. Table 8-37. TDR Control Register (TDRCR), address 0x0C01 BIT NAME 15:11 DEFAULT FUNCTION Reserved 0x02,RO Ignore on read 10 cfg_tdr_tx_mode 0x1,RW 1 – Enable TDR TX transmission mode 9 Reserved 0,RW Reserved 8:6 cfg_soft_avr_cycles 0x7,RW Number of averaging cycles: 0x0 – TDR disabled. 0x1 – 1 TDR cycle (no averaging). 0x2 – 2 TDR cycles.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 8.5.12 TDR Low Threshold Register (TDRLT3) This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test. Table 8-41. TDR Low Threshold Register (TDRLT3), address 0x0C05 BIT 15 14:8 7 6:0 NAME Reserved DEFAULT 0,RO cfg_ptrn_low_th_5 Reserved 0x4,RW 0,RO cfg_ptrn_low_th_4 0x5,RW FUNCTION Ignore on read Peak (absolute) low threshold value 5, for TX pattern.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.5.15 TDR High Threshold Register (TDRHT2) This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test. Table 8-44. TDR High Threshold Register (TDRHT2), address 0x0C08 BIT NAME 15 DEFAULT Reserved 14:8 cfg_ptrn_High_th_3 7 Ignore on read 0x4A,RW Reserved 6:0 FUNCTION 0,RO Peak (absolute) High threshold value 3, for TX pattern.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com 8.5.19 TDR Pattern Control Register 2 (TDRLCR2) This register allows configuring the gear threshold values for the TDR test. Table 8-48. TDR Pattern Control Register 2 (TDRLCR2), address 0x0C0C BIT NAME DEFAULT 15:9 Reserved 8:4 cfg_ptrn_gear_tout 3:0 Reserved FUNCTION 0,RO Ignore on read 0x14,RW Thresholds gear shifts distance in samples 0x8,RO Ignore on read 8.5.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.5.24 DSA Output Control (DSAOCR) This register configures which DSA outputs are selected to the 16 bit RAM available bits. The files configure the MSB location of the DSA engine. Table 8-53. DSA Output Control (DSAOCR), address 0x0C2A BIT NAME 15:12 cfg_dsa_output_msb 11:0 Reserved DEFAULT FUNCTION 0x0,RW DSA output MSB select. Select which bits of the DSA output are saved in the RAM 0x003,RO Reserved 8.5.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 8.5.29 www.ti.com CD Pre Test Configuration Control 2 (CDPTC2R) This register latches the outcome of enabling the cable diagnostic pre test configuration. Table 8-58.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 9 Electrical Specifications All parameters are derived by test, statistical analysis, or design. ABSOLUTE MAXIMUM RATINGS (1) 9.1 VALUE UNIT –0.3 to 3.8 V V18_PFBIN1, V18_PFBIN2 –0.3 to 2.2 V VA11_PFBIN1, VA11_PFBIN2 –0.3 to 1.8 V –0.3 to 2.2 V –0.3 to 6 V –0.3 to 3.8 V –0.3 to 2.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 9.4 www.ti.
TLK100 www.ti.com 9.6 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 AC Specifications Table 9-1. Power Up Timing PARAMETER TEST CONDITIONS t1 Reset deassertion time from power up t2 Time from reset deassertion to the hardware configuration pins transition to output drivers VCC MIN Hardware Configuration Pins are described in the Pin Description section.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-3. MII Serial Management Timing PARAMETER TEST CONDITIONS t1 MDC Frequency t2 MDC to MDIO (Output) Delay Time t3 t4 MIN TYP MAX UNIT 2.5 25 MHz 0 ns MDIO (Input) to MDC Hold Time 10 ns MDIO (Input) to MDC Setup Time 10 ns MDC t1 t2 MDIO (Output) MDC t3 t4 MDIO (Input) Valid Data T0340-01 Figure 9-3. MII Serial Management Timing Table 9-4.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 9-5. 100Mb/s MII Receive Timing PARAMETER (1) TEST CONDITIONS t1 RX_CLK High Time t2 RX_CLK Low Time t3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay (1) MIN TYP MAX UNIT 100 Mb/s Normal mode 16 20 24 ns 100 Mb/s Normal mode 10 30 ns RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-7. 100BASE-TX Transmit Packet Deassertion Timing PARAMETER t1 TEST CONDITIONS TX_CLK to PMD Output Pair deassertion MIN TYP 100 Mb/s Normal mode MAX UNIT 8.6 bits TX_CLK TX_EN TXD t1 PMD Output Pair (T/R) DATA DATA (T/R) IDLE IDLE T0344-01 Figure 9-7. 100BASE-TX Transmit Packet Latency Timing Table 9-8.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 9-9. 100BASE-TX Receive Packet Latency Timing TEST CONDITIONS (1) PARAMETER t1 t2 (1) (2) (3) Carrier Sense ON Delay (2) Receive Data Latency MIN TYP MAX UNIT 100 Mb/s Normal mode 13.6 bits (3) 100 Mb/s Normal mode 18.4 bits PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-11. 10 Mb/s MII Transmit Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10 Mb/s MII mode 190 200 210 ns t1 TX_CLK Low Time t2 TX_CLK High Time t3 TXD[3:0], TX_EN Data Setup to TX_CLK ↓ 10 Mb/s MII mode 25 ns t4 TXD[3:0], TX_EN Data Hold from TX_CLK ↑ 10 Mb/s MII mode 0 ns t2 t1 TX_CLK t3 TXD[3:0] TX_EN t4 Valid Data T0348-01 Figure 9-11. 10 Mb/s MII Transmit Timing Table 9-12.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 9-13. 10BASE-T Transmit Timing (Start of Packet) PARAMETER t1 (1) TEST CONDITIONS Transmit Output Delay from the Falling Edge of TX_CLK MIN 10 Mb/s MII mode TYP MAX UNIT (1) 5.8 bits (1) 1 bit time = 100ns in 10Mb/s. TX_CLK TX_EN TXD t1 PMD Output Pair Figure 9-13. 10BASE-T Transmit Timing (Start of Packet) Table 9-14.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-15. 10BASE-T Receive Timing (Start of Packet) PARAMETER TEST CONDITIONS MIN TYP MAX 1000 UNIT t1 Carrier Sense Turn On Delay (PMD Input Pair to MII_CRS) 550 t2 RX_DV Latency (1) 9.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 9-17. 10Mb/s Jabber Timing PARAMETER t1 TEST CONDITIONS MIN Jabber Activation Time TYP MAX 100 UNIT ms TXE t1 PMD Output Pair T0357-01 Figure 9-17. 10Mb/s Jabber Timing Table 9-18. 10BASE-T Normal Link Pulse Timing PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT t1 Pulse Period 16 ms t2 Pulse Width 100 ns (1) Transmit timing t1 t2 Normal Link Pulse(s) T0358-01 Figure 9-18.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-20. 100BASE-TX Signal Detect Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 SD Internal Turn-on Time 100 μs t2 SD Internal Turn-off Time 500 μs PMD Input Pair t1 t2 SD+ Intermal T0360-01 NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant. Figure 9-20. 100BASE-TX Signal Detect Timing Table 9-21.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 Table 9-22. 10 Mb/s Internal Loopback Timing PARAMETER t1 TEST CONDITIONS TX_EN to RX_DV Loopback MIN TYP MAX 10 Mb/s internal loopback mode 2.4 UNIT μs TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0362-01 NOTE: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. Figure 9-22. 10 Mb/s Internal Loopback Timing Table 9-23.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Table 9-24. 25 MHz_OUT Timing PARAMETER (1) t1 25 MHz_OUT t2 25 MHz_OUT (1) High Time t3 25 MHz_OUT (1) Low Time (1) TEST CONDITIONS propagation delay MIN TYP Relative to XI MAX 8.8 20 MII mode UNIT ns ns 20 25 MHz_OUT characteristics are dependent upon the XI input characteristics. XI t1 t2 t3 25 MHz_OUT T0366-01 Figure 9-24. 25 MHz_OUT Timing Table 9-25.
TLK100 www.ti.com SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 10 Appendix A: Digital Spectrum Analyzer (DSA) Output The following figure is an example of the DSA output. In the figure, 512 samples of the spectral analysis of 4 different cable lengths are provided. The first bin is 23.4 MHz. Each following bin represents 61kHz increment. A view of the LPF nature of the channel and how it increases as longer cables are used is seen.
TLK100 SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from A Revision (August 2009) to B Revision ................................................................................................ Page • • • • • • 84 Added bullet item " Enables IEEE1588 Time-Stamping" .......................................................................
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