TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver Check for Samples: TLK105, TLK106 1 Introduction 1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com MII Option RMII Option MII/RMII Interface Cable Diagnostics (TLK106 only) Figure 1-1.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 2 Pin Descriptions The TLK10x pins fall into the following interface categories (subsequent sections describe each interface): • • • • Serial Management Interface MAC Data Interface Clock Interface LED Interface • • • • • Reset and Power Down Bootstrap Configuration Inputs 10/100Mbs PMD Interface Special Connect Pins Power and Ground pins Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 This document describes signals that take on different names depending on configuration. In such cases, the different names are placed together and separated by slash (/) characters. For example, "RXD_3 / PHYAD4". Active low signals are represented by overbars. 2.2 Serial Management Interface (SMI) PIN NAME NO. TYPE DESCRIPTION MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 2.4 www.ti.com 10Mbs and 100Mbs PMD Interface PIN NAME TYPE NO. DESCRIPTION Differential common driver transmit output (PMD Output Pair): These differential outputs are automatically configured to either 10Base-T or 100Base-TX signaling. TD–, TD+ 11, 12 I/O In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation.
TLK105 TLK106 www.ti.com 2.8 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Power and Bias Connections PIN NAME NO. TYPE DESCRIPTION RBIAS 16 I Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND. PFBOUT 15 O Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT. In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 13 and pin 24). See Figure 3-1 for proper placement.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 PIN www.ti.com TYPE NAME NO. DESCRIPTION AMDIX_EN (RX_ER) 28 S, O, PU This option sets the Auto-MDIX mode. By default, it enables Auto-MDIX. An external pulldown resistor disables Auto-MDIX mode. MII_MODE (RX_DV) 26 S, O, PD MII Mode Select: This option selects the operating mode of the MAC data interface. This pin has a weak internal pull-down, and it defaults to normal MII operation mode.
TLK105 TLK106 www.ti.com 3.2.2 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Dual Supply Operation When a 1.55V external power rail is available, the TLK10x can be configured as shown in Figure 3-2. PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2 (pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing ‘1’ to bit 15 of the VRCR register (0x00d0h). 3.3V Supply 10mF 3.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 3.4 www.ti.com Auto-Negotiation The TLK10x device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation enabled, the TLK10x negotiates with the link partner to determine the speed and duplex mode. If the link partner cannot Auto-Negotiate, the TLK10x device enters parallel-detect mode to determine the speed of the link partner. Parallel-detect mode uses fixed half-duplex mode.
TLK105 TLK106 www.ti.com 3.6 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 MII Isolate Mode The TLK10x can be put into MII-Isolate mode by writing bit 10 of the BMCR register. When in the MII-Isolate mode, the TLK10x ignores packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in isolate mode, the TLK10x continues to respond to all management transactions.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 3.8 www.ti.com LED Interface The TLK10x supports one configurable Light Emitting Diode (LED) pin. The device supports 2 LED configurations: Link and Activity. Functions are multiplexed into two modes. The LED can be controlled by configuration pin and internal register bits. Bit 5 of the PHY Control register (PHYCR) selects the LED mode as described in Table 3-3. Table 3-3.
TLK105 TLK106 www.ti.com 3.9 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Loopback Functionality The TLK10x provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK10x digital and analog data path. Generally, the TLK10x may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. 3.9.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 3.9.2 www.ti.com Far-End Loopback Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-6 shows Far-end loopback functionality.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 3.10 BIST The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loop back using a cable fixture.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (for example, CAT5, CAT5e, or CAT6).
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 4 Interfaces 4.1 Media Independent Interface (MII) The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22. The MII signals are summarized below.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 4.2 www.ti.com Reduced Media Independent Interface (RMII) TLK10x incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 PHY TX_EN TXD[1:0] RX_CLK RX_DV RX_ER RXD[1:0] CRS/RX_DV MAC TX_EN TXD[1:0] RX_CLK (optional) RX_DV (optional) RX_ER RXD[1:0] CRS/RX_DV XI 50MHz Clock Source Figure 4-2. TLK10x RMII/MAC Connection RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 4.3 www.ti.com Serial Management Interface The Serial Management Interface (SMI), provides access to the TLK10x internal registers space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002 in addition to several others, providing additional visibility and controllability of the TLK10x device.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 For write transactions, the station-management entity writes data to the addressed TLK10x, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4. Table 4-2.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 4.3.1 www.ti.com Extended Address Space Access The TLK10x SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.
TLK105 TLK106 www.ti.com 4.3.1.3 To 1. 2. 3. 4. SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Write (no post increment) Operation write an extended register set register: Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. Write the desired register address to register ADDAR. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR. Write the content of the desired extended register set register to register ADDAR.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 5 Architecture The TLK10x Fast Ethernet transceiver is a physical layer core for Ethernet 100Base-TX and 10Base-T applications. The TLK10x contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 TX_CLK TX_EN TXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code RX_CLK RX_DV RXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code Don't Care RX_ER Figure 5-2. Transmit Code Error Forwarding Diagram 5.1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 5-1.
TLK105 TLK106 www.ti.com 5.1.5 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Digital to Analog Converter The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 5.2.5 www.ti.com Descrambler The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100BTX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 5.2.10 Signal Detect The signal detect function of the TLK10x is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters. The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 5.3.4 www.ti.com Jabber Function Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK10x output and disables the transmitter if it attempts to transmit a packet of longer than legal size.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 When auto negotiation has started, the TLK10x transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com First Link Failure Occurrence Valid Data LOW Quality Data / Link Loss Signal Link Drop T1 Link Loss Indication (Link LED) Figure 5-3. TLK10x Link Loss Mechanism As described in Figure 5-3, the TLK10x link loss mechanism is based on a time window search period, in which the signal behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 6 Reset and Power Down Operation The TLK10x includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up. At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 6.4 www.ti.com Power Save Modes The TLK10x supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available).
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 7 Design Guidelines 7.1 TPI Network Circuit Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Below is a partial list of recommended transformers. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application. • • Pulse H1102 Pulse HX1188 Vdd Common-mode chokes may be required. RD– 49.9 W Vdd 1:1 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 7.2.2 www.ti.com Crystal The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW.
TLK105 TLK106 www.ti.com 7.3 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Thermal Vias Recommendation The following thermal via guidelines apply to DOWN_PAD, pin 33: 1. Thermal via size = 0.2mm 2. Recommend 4 vias 3. Vias have a center to center separation of 2mm. Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 7-3 illustrates an example layout. Figure 7-3.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 8 Register Block Table 8-1.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-2.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-3.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-3.
TLK105 TLK106 www.ti.com 8.1 Register Definition In • • • • • • • • • • 8.1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 (continued) BIT BIT NAME DEFAULT DESCRIPTION 0 = Normal operation Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it self-clears.
TLK105 TLK106 www.ti.com 8.1.2 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Basic Mode Status Register (BMSR) Table 8-5. Basic Mode Status Register (BMSR), address 0x0001 BIT BIT NAME DEFAULT 15 100Base-T4 0, RO/P 14 100Base-TX Full Duplex 1, RO/P 100Base-TX Half Duplex 1, RO/P 10Base-T Full Duplex 1, RO/P 10Base-T Half Duplex 1, RO/P DESCRIPTION 100Base-T4 Capable: This protocol is not available. Always 0 = Device does not perform 100Base-T4 mode.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.1.3 www.ti.com PHY Identifier Register 1 (PHYIDR1) The PHY Identifier Registers 1 and 2 together form a unique identifier for the TLK10x. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
TLK105 TLK106 www.ti.com 8.1.5 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation. Table 8-8.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.1.6 www.ti.com Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 8-9.
TLK105 TLK106 www.ti.com 8.1.7 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 8-10. Auto-Negotiate Expansion Register (ANER), address 0x0006 BIT BIT NAME 15:5 RESERVED 4 PDF DEFAULT DESCRIPTION 0, RO RESERVED: Writes ignored, Read as 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.1.8 www.ti.com Auto-Negotiate Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-11.
TLK105 TLK106 www.ti.com 8.1.9 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-12.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 8.1.10 Control register 1 (CR1) Table 8-13. Control register 1 (CR1), address 0x0009 BIT 15:10 9 BIT NAME DEFAULT DESCRIPTION RESERVED 1, RW RESERVED RMII Enhanced Mode 0, RW RMII Enhanced Mode: 1 = Enable RMII Enhanced Mode 0 = RMII operates in normal mode In normal mode, If the line is not idle CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to “2”.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-13. Control register 1 (CR1), address 0x0009 (continued) BIT BIT NAME 3:2 Fast AN Sel DEFAULT 0, RW DESCRIPTION Fast Auto-Negotiation Select bits: Fast AN Select Break Link Timer Link Fail Inhibit Timer Auto-Neg Wait Timer <00> 80 50 35 <01> 120 75 50 <10> 240 150 100 <11> NA NA NA Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 8.1.11 Control register 2 (CR2) Table 8-14. Control register 2 (CR2), address 0x000A BIT BIT NAME DEFAULT DESCRIPTION 15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.1.12 Control Register 3 (CR3) Table 8-15. Control register 3 (CR3), address 0x000B BIT BIT NAME 15:7 RESERVED 6 Polarity Swap DEFAULT DESCRIPTION 0, RO RESERVED: Writes ignored, read as 0. 0, RW Polarity Swap: 1 = Inverted polarity on both pairs: TPTD+ ↔ TPTD-, TPRD+ ↔ TPRD0 = Normal polarity Port Mirror function: To Enable port mirroring, set bit 5 and this bit high.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-16. Register Control Register (REGCR), address 0x000D BIT BIT NAME 15:14 Function 13:5 4:0 8.2.2 DEFAULT DESCRIPTION 0, RW 00 01 10 11 = Address = Data, no post increment = Data, post increment on read and write = Data, post increment on write only RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 www.ti.com 8.3 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 PHY Status Register (PHYSTS) This register provides quick access to commonly accessed PHY control status and general information. Table 8-18. PHY Status Register (PHYSTS), address 0x0010 BIT NAME DEFAULT 15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-18.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011 (continued) BIT NAME DEFAULT DESCRIPTION 11 Scrambler Bypass 0,RW 10 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 (continued) BIT DEFAULT DESCRIPTION 11 Duplex Mode Changed INT NAME 0,RO, COR Change of duplex status interrupt: 1 = Duplex status change interrupt is pending 0 = No change of duplex status 10 Auto-Negotiation Completed INT 0,RO, COR Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-21.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-24.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-25. RMII Control and Status Register (RCSR), address 0x0017 (continued) BIT 4 NAME RMII Revision Select DEFAULT 0,RW DESCRIPTION RMII Revision Select: 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 8.11 LED Control Register (LEDCR) This register provides the ability to directly manually control the Link LED output. Table 8-26. LED Control Register (LEDCR), address 0x0018 BIT NAME 15:11 RESERVED 10:9 Blink Rate DEFAULT DESCRIPTION <0000 0>, ro RESERVED: Writes ignored, read as 0.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued) BIT NAME DEFAULT 5 LED CFG <0>, RW, Pin_Strap DESCRIPTION LED Configuration Modes: Mode 4:0 PHY ADDR <0000 1>, RO LED_CFG 1 1 2 0 LED_LINK ON for Good Link OFF for No Link ON for Good Link BLINK for Activity PHY Address: Strapping configuration for PHY Address. 8.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-29. BIST Control and Status Register 1 (BICSR1), address 0x001B (continued) BIT 7:0 BIT NAME BIST IPG Length DEFAULT DESCRIPTION <0111 1101>, RW BIST IPG Length: Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D which is equal to 125 bytes 8.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.16 Cable Diagnostic Control Register (CDCR) Table 8-31. Cable Diagnostic Control Register (CDCR), address 0x001E BIT NAME DEFAULT FUNCTION 15 Diagnostic Start 0,RW Cable Diagnostic Process Start: 1 = Start execute cable measurement 0 = Cable Diagnostic is disabled Diagnostic Start bit is cleared with raise of Diagnostic Done indication. <000 00>,RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042 (continued) BIT NAME DEFAULT FUNCTION 3:0 Phase Shift Value <0000>,RW TX Clock Phase Shift Value: The value of this register represents the current phase shift between Reference clock at XI and MII Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4 times the difference (in nSec).
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-36. Cable Diagnostic Specific Control Register (CDSCR), address 0x0170 (continued) BIT BIT NAME DEFAULT DESCRIPTION 14 Diagnostic Cross Disable 0,RW Cross TDR Diagnostic mode 1 = Disable TDR Cross mode – TDR will be executed in regular mode only 0 = Diagnostic of crossing pairs is enabled In Cross Diagnostic mode, the TDR mechanism is looking for reflection on the other pair to check short between pairs.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com Table 8-40. Cable Diagnostic Location Results Register 1 (CDLRR1), address 0x0180 (continued) BIT NAME DEFAULT FUNCTION 7:0 TPTD Peak Location 1 <0000 0000>, RO Location of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY 8.20.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 8.20.8 Cable Diagnostic Amplitude Results Register 1 (CDARR1) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-45. Cable Diagnostic Amplitude Results Register 1 (CDARR1), address 0x0185 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 8.20.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-48. Cable Diagnostic Amplitude Results Register 4 (CDARR4), address 0x0188 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 Table 8-50. Cable Diagnostic General Results Register (CDGRR), address 0x018A (continued) BIT NAME DEFAULT FUNCTION 3 Above 5 TPTD Peaks 0,RO More than 5 reflections were detected on TPTD 2 Above 5 TPRD Peaks 0,RO More than 5 reflections were detected on TPRD RESERVED <00>,RO RESERVED: Writes ignored, read as 0 1:0 8.20.14 ALCD Control and Results 2 (ALCDRR2) Table 8-51.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9 Electrical Specifications All parameters are derived by test, statistical analysis, or design. ABSOLUTE MAXIMUM RATINGS (1) 9.1 VDD33_IO, AVDD33 Supply voltage PFBIN1, PFBIN2 DC Input voltage –0.3 to 3.8 XO DC Output voltage –0.3 to 3.8 Other outputs V –0.3 to 3.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS θJA Junction-to-ambient thermal resistance (no airflow) θJB Junction-to-board thermal resistance θJC(Top) Junction-to-case thermal resistance, Top θJC(Bottom) Junction-to-case thermal resistance, Bottom 9.4 MIN TYP JEDEC high-K model MAX UNIT 36.4 9.3 °C/W 26.8 1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.5 www.ti.com POWER SUPPLY CHARACTERISTICS The data was measured using a TLK10x evaluation board. The current from each of the power supplies is measured and the power dissipation is computed. For the single 3.3V external supply case the power dissipation across the internal linear regulator is also included. All the power dissipation numbers are measured at the nominal power supply and typical temperature of 25°C.
TLK105 TLK106 www.ti.com 9.6 9.6.1 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 AC Specifications Power Up Timing Table 9-1. Power Up Timing PARAMETER t1 TEST CONDITIONS Time from powerup to hardware-configuration pin transition to output-driver function, using internal POR (RESET pin tied high) MIN TYP MAX 100 270 UNIT ms VDD Hardware RESET t1 Dual function pins Become enabled As outputs Figure 9-1.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.3 www.ti.com MII Serial Management Timing Table 9-3. MII Serial Management Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.5 25 MHz 30 ns t1 MDC Frequency t2 MDC to MDIO (Output) Delay Time t3 MDIO (Input) to MDC Hold Time 10 ns t4 MDIO (Input) to MDC Setup Time 10 ns 0 MDC t1 t2 MDIO (Output) MDC t3 t4 MDIO (Input) Valid Data T0340-01 Figure 9-3. MII Serial Management Timing 9.6.
TLK105 TLK106 www.ti.com 9.6.5 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 100Mb/s MII Receive Timing Table 9-5. 100Mb/s MII Receive Timing PARAMETER (1) TEST CONDITIONS t1 RX_CLK High Time t2 RX_CLK Low Time t3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay (1) MIN TYP MAX UNIT 100Mbs Normal mode 16 20 24 ns 100Mbs Normal mode 10 30 ns RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.7 www.ti.com 100Base-TX Transmit Packet Deassertion Timing Table 9-7. 100Base-TX Transmit Packet Deassertion Timing PARAMETER t1 TEST CONDITIONS TX_CLK to PMD Output Pair deassertion MIN 100Mbs Normal mode TYP 4.6 MAX UNIT bits TX_CLK TX_EN TXD t1 PMD Output Pair DATA DATA (T/R) (T/R) IDLE IDLE T0344-01 Figure 9-7.
TLK105 TLK106 www.ti.com 9.6.8 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 100Base-TX Transmit Timing (tR/F and Jitter) Table 9-8. 100Base-TX Transmit Timing (tR/F and Jitter) PARAMETER t1 t2 (1) (2) TEST CONDITIONS MIN TYP MAX 3 4 5 ns 100Mbs tR and tF Mismatch (2) 500 ps 100Mbs PMD Output Pair Transmit Jitter 1.4 ns 100Mbs PMD Output Pair tR and tF (1) UNIT Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.9 www.ti.com 100Base-TX Receive Packet Latency Timing Table 9-9.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.11 10Mbs MII Transmit Timing Table 9-11. 10Mbs MII Transmit Timing PARAMETER MIN TYP MAX UNIT 10Mbs MII mode 190 200 210 ns TXD[3:0], TX_EN Data Setup to TX_CLK ↑ 10Mbs MII mode 25 ns TXD[3:0], TX_EN Data Hold from TX_CLK ↑ 10Mbs MII mode 0 ns t1 TX_CLK Low Time t2 TX_CLK High Time t3 t4 TEST CONDITIONS An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9.6.13 10Base-T Transmit Timing (Start of Packet) Table 9-13. 10Base-T Transmit Timing (Start of Packet) PARAMETER t1 (1) TEST CONDITIONS Transmit Output Delay from the Falling Edge of TX_CLK MIN 10Mbs MII mode TYP MAX 5.8 UNIT (1) bits (1) 1 bit time = 100ns in 10Mb/s. TX_CLK TX_EN TXD t1 PMD Output Pair Figure 9-13. 10Base-T Transmit Timing (Start of Packet) 9.6.14 10Base-T Transmit Timing (End of Packet) Table 9-14.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.15 10Base-T Receive Timing (Start of Packet) Table 9-15.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9.6.17 10Mb/s Jabber Timing Table 9-17. 10Mb/s Jabber Timing PARAMETER t1 Jabber Activation Time t2 Jabber Deactivation Time TEST CONDITIONS MIN TYP MAX 100 10 Mb/s MII mode UNIT ms 500 TX_EN t1 PMD Output Pair t2 COL Figure 9-17. 10Mb/s Jabber Timing 9.6.18 10Base-T Normal Link Pulse Timing Table 9-18.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.19 Auto-Negotiation Fast Link Pulse (FLP) Timing Table 9-19.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9.6.20 100Base-TX Signal Detect Timing Table 9-20. 100Base-TX Signal Detect Timing MAX UNIT t1 SD Internal Turn-on Time PARAMETER TEST CONDITIONS MIN TYP 100 μs t2 Internal Turn-off Time 200 μs PMD Input Pair t1 t2 SD+ Intermal T0360-01 NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant. Figure 9-20. 100Base-TX Signal Detect Timing 9.6.21 100Mbs Loopback Timing Table 9-21.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0361-01 (1) (2) (3) (4) Due to the nature of the descrambler function, all 100Base-TX Loopback modes cause an initial dead-time of up to 550 μs during which time no data is present at the receive MII outputs. The 100Base-TX timing specified is based on device delays after the initial 550µs dead-time.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9.6.22 10Mbs Internal Loopback Timing Table 9-22. 10Mbs Internal Loopback Timing PARAMETER t1 TEST CONDITIONS TX_EN to RX_DV Loopback MIN TYP 10Mbs internal loopback mode MAX UNIT μs 1.7 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0362-01 (1) (2) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. Analog loopback was used. Looping the TX to RX at the analog input/output stage.
TLK105 TLK106 www.ti.com SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 9.6.24 RMII Receive Timing Table 9-24. RMII Receive Timing PARAMETER TEST CONDITIONS MIN XI Clock Period t2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising t3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 17.6 t4 CRS OFF delay From TR symbol on PMD Receive Pair to initial assertion of CRS_DV 26.2 t5 RXD[1:0] and RX_ER latency From symbol on Receive Pair.
TLK105 TLK106 SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013 www.ti.com 9.6.25 Isolation Timing Table 9-25. Isolation Timing PARAMETER t1 TEST CONDITIONS MIN TYP MAX From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 71 UNIT ns H/W or S/W Reset t1 ISOLATE MODE NORMAL T0365-01 Figure 9-25. Isolation Timing 9.6.26 25MHz_OUT Clock Timing Table 9-26.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TLK105RHBR VQFN RHB 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLK105RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLK106RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK105RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLK105RHBT VQFN RHB 32 250 210.0 185.0 35.0 TLK106RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLK106RHBT VQFN RHB 32 250 210.0 185.0 35.
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