Datasheet

TLK110
www.ti.com SLLS901C –DECEMBER 2011–REVISED JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1 Introduction .............................................. 1 6 Reset and Power Down Operation ................. 37
1.1 Features ............................................. 1 6.1 Hardware Reset .................................... 37
1.2 Applications .......................................... 1 6.2 Software Reset ..................................... 37
1.3 Device Overview ..................................... 2 6.3 Power Down/Interrupt .............................. 37
2 Pin Descriptions ......................................... 4 6.4 Power Save Modes ................................. 38
2.1 Pin Layout ........................................... 4 7 Design Guidelines ..................................... 39
2.2 Serial Management Interface (SMI) ................. 4 7.1 TPI Network Circuit ................................. 39
2.3 MAC Data Interface .................................. 5 7.2 Clock In (XI) Requirements ......................... 39
2.4 10Mbs and 100Mbs PMD Interface .................. 6 8 Register Block ......................................... 41
2.5 Clock Interface ....................................... 6 8.1 Register Definition .................................. 46
2.6 LED Interface ........................................ 6 8.2 Extended Register Addressing ..................... 59
2.7 JTAG Interface ....................................... 6 8.3 PHY Status Register (PHYSTS) ................... 61
2.8 Reset and Power Down ............................. 7 8.4 PHY Specific Control Register (PHYSCR) ......... 62
2.9 Power and Bias Connections ........................ 7 8.5 MII Interrupt Status Register 1 (MISR1) ............ 63
3 Hardware Configuration ............................... 7 8.6 MII Interrupt Status Register 2 (MISR2) ............ 64
3.1 Bootstrap Configuration .............................. 8 8.7 False Carrier Sense Counter Register (FCSCR) ... 65
3.2 Power Supply Configuration ......................... 9 8.8 Receiver Error Counter Register (RECR) .......... 65
3.3 IO Pins Hi-Z State During Reset ................... 11 8.9 BIST Control Register (BISCR) .................... 66
3.4 Auto-Negotiation .................................... 11 8.10 RMII Control and Status Register (RCSR) ......... 67
3.5 Auto-MDIX .......................................... 12 8.11 LED Control Register (LEDCR) .................... 68
3.6 MII Isolate Mode .................................... 12 8.12 PHY Control Register (PHYCR) .................... 68
3.7 PHY Address ....................................... 12 8.13 10Base-T Status/Control Register (10BTSCR) .... 69
3.8 Software Strapping Mode .......................... 14 8.14 BIST Control and Status Register 1 (BICSR1) ..... 70
3.9 LED Interface ....................................... 16 8.15 BIST Control and Status Register2 (BICSR2) ..... 70
3.10 Loopback Functionality ............................. 17 8.16 Cable Diagnostic Control Register (CDCR) ........ 71
3.11 BIST ................................................ 19 8.17 PHY Reset Control Register (PHYRCR) ........... 71
3.12 Cable Diagnostics .................................. 19 8.18 TX_CLK Phase Shift Register (TXCPSR) .......... 71
4 Interfaces ................................................ 21 8.19 Voltage Regulator Control Register (VRCR) ....... 72
4.1 Media Independent Interface (MII) ................. 21 8.20 Cable Diagnostic Configuration/Result Registers .. 72
4.2 Reduced Media Independent Interface (RMII) ..... 22 9 Electrical Specifications ............................. 78
4.3 Serial Management Interface ....................... 23 9.1 ABSOLUTE MAXIMUM RATINGS ................. 78
9.2 RECOMMENDED OPERATING CONDITIONS
5 Architecture ............................................. 27
9.3 48-Pin Industrial Device Thermal Characteristics
5.1 100Base-TX Transmit Path ......................... 27
9.4 DC CHARACTERISTICS, VDD_IO
5.2 100Base-TX Receive Path ......................... 30
9.5 DC CHARACTERISTICS
5.3 10Base-T Receive Path ............................ 32
9.6 POWER SUPPLY CHARACTERISTICS
5.4 Auto Negotiation .................................... 33
9.7 AC Specifications
5.5 Link Down Functionality ............................ 35
Revision History
Copyright © 2011–2013, Texas Instruments Incorporated Contents 3
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