Datasheet

TLK110
SLLS901C –DECEMBER 2011–REVISED JUNE 2013 www.ti.com
8.14 BIST Control and Status Register 1 (BICSR1)
This register provides the total number of error bytes that was received by the PRBS checker and defines
the Inter packet Gap (IPG) for the packet generator.
Table 8-29. BIST Control and Status Register 1 (BICSR1), address 0x001B
BIT BIT NAME DEFAULT DESCRIPTION
15:8 BIST Error 0, RO BIST Error Count:
Count Holds number of erroneous bytes that were received by the PRBS checker. Value in this
register is locked when write is done to bit[0] or bit[1] (see below).
When PRBS Count Mode set to zero, count stops on 0xFF. See BISCR register (0x0016) for
further details
Note: Writing “1” to bit 15 will lock counter ’s value for successive read operation and clear the
BIST Error Counter.
7:0 BIST IPG <0111 1101>, BIST IPG Length:
Length RW Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive
packets generated by the BIST. Default value is 0x7D which is equal to 125 bytes
8.15 BIST Control and Status Register2 (BICSR2)
This register allows programming the length of the generated packets in bytes for the BIST mechanism.
Table 8-30. BIST Control and Status Register 2 (BICSR2), address 0x001C
BIT BIT NAME DEFAULT DESCRIPTION
15:11 RESERVED <0000 0>, RESERVED: Writes ignored, read as 0.
RO
10:0 BIST Packet 0X5DC,RW BIST Packet Length:
Length Length of the generated BIST packets. The value of this register defines the size (in bytes) of
every packet that generated by the BIST. Default value is 0x5DC which is equal to 1500 bytes
70 Register Block Copyright © 2011–2013, Texas Instruments Incorporated
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