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TLK2541

www.ti.com

SLLS779B –JANUARY 2008– REVISED APRIL 2008

1 TO 2.6 GBPS TRANSCEIVER

Check for Samples: TLK2541

FEATURES

• Receiver Differential Input Thresholds 200 mV

Minimum

• 1 to 2.6 Gigabits Per Second (Gbps)

Serializer/Deserializer • 3 V Tolerance on Parallel Data Input Signals

• Independent Transmit/Receive Channels for • Selectable 10 or 20 bit Parallel TTL Compatible

Asynchronous Data Rate Operation Data Interface

• Fast Relock at 1.25 Gbps and 2.5 Gbps for • Industrial Temperature Range –40°C to 85°C

EPON OLT Applications

• Integrated 50-Ω Termination Resistors on RX

• Hot-Plug Protection

• Transmit FIFO Decouples Transmit Clock

• High-Performance 80-Pin TQFP Package (PFP) From Reference Clock

• 2.5-V Power Supply for Low Power Operation

APPLICATIONS

• Programmable Preemphasis Levels on Serial

• Next Generation EPON OLT Systems

Output

• Ideal for use with EPON OLT MAC Solutions

• Interfaces to Backplane, Copper Cables, or

such as TK3723 from Teknovus

Optical Converters

• Gigabit Ethernet and Fibre Channel Links

• On-Chip 8-bit/10-bit Encoding/Decoding

• On-Chip PLL Provides Clock Synthesis From

Low-Speed Reference

DESCRIPTION

The TLK2541 is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use in

high-speed bidirectional point-to-point data transmission systems. The TLK2541 supports an effective serial

interface speed of 1 Gbps to 1.3 Gbps or 2 to 2.6 Gbps, providing over 2 Gbps of data bandwidth.

The primary application of this chip is to provide high-speed I/O data channels for point-to-point baseband data

transmission over controlled impedance media of approximately 50Ω. The transmission media can be

printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is

dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The

TLK2541 allows for independent transmit and receive data rate operation for applications that need asymmetrical

data rates such as Passive Optical Networking.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the

number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is

delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance

backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and

cost savings over parallel solutions, as well as scalability for higher data rates.

At full rate, the TLK2541 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction

functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of

2.6 Gbps. The transmitter latches 20 parallel data at a rate based on the supplied transmit clock (TX_CLK).. The

20-bit word is then transmitted differentially at 20 times the reference clock (REFCLK) rate. The receiver section

performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data

to the recovered clock (RX_CLK). It then outputs the 20 bit recovered word on the receive data terminals

RXD[0:19]. If the internal 8B/10B coding and decoding logic is enabled, 16 bits of data and two bits of control are

latched on TX_CLK and the data is encoded into a 20 bit data word to be serialized. Likewise the 20 bit received

data word is decoded into a 16 bit data word plus two bits of decode status.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com 1 TO 2.6 GBPS TRANSCEIVER Check for Samples: TLK2541 FEATURES 1 • 2 • • • • • • • • • 1 to 2.6 Gigabits Per Second (Gbps) Serializer/Deserializer Independent Transmit/Receive Channels for Asynchronous Data Rate Operation Fast Relock at 1.25 Gbps and 2.5 Gbps for EPON OLT Applications Hot-Plug Protection High-Performance 80-Pin TQFP Package (PFP) 2.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) At half rate, the TLK2541 only uses half of the parallel transmit and receive data busses. 10 bits of data on TXD[0:9] are latched by TX_CLK and serialized.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com BLOCK DIAGRAM TX_FIFO PRBS Generator REFCLK CTRL0, CTRL1, RXCODE LCKREFN PRBSPASS RX_CLK SYNCEN Figure 1.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE DESCRIPTION Serial Transmit Outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 10 or 20 times the TX_CLK value. DOUTTXP and DOUTTXN are put in a high impedance state when LOOPEN is high and are active when LOOPEN is low. When Disabled or during power-on-reset these pins are high impedance.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME RXRATE NO. 64 TYPE Input (w/Pull-up) DESCRIPTION Receive Rate Select. When pulled high or left unconnected, the receive path expects to operate at a data rate of approximately 20 times REFCLK. This provides a data rate range of 2.0 to 2.6 Gbps. In this mode, the width of the receive parallel bus is 2 Bytes, either 20 bit coded data or 16 bit date plus two K-status bits of un-coded data.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com Table 1. Test Pin Descriptions SIGNAL LCKREFN PIN # TYPE 30 DESCRIPTION Lock to Reference. When the LCKREFN pin is asserted active low, the tracking circuitry on the receiver Clock/Data Recovery (CDR) circuit is disabled and the recovered byte clock will become a buffered version of REFCLK. Input (w/Pull-up) LOOPEN 26 Input (w/Pull-down) Loop Enable. When LOOPEN is active high, the internal loop-back path is activated.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com DISSIPATION RATINGS (1) (1) (2) (3) PACKAGE (2) TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING PFP80 (3) 5.01 W 42.9 mW/°C 2.69 W This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4 layer 3 in × 3 in PCB. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com TTL INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted), TTL signals: TXD[0:19], TX_CLK, LOOPEN, ENABLE, PRBS_EN, PRE , CTRL0, CTRL1, TXRATE, RXRATE, REFCLK, LCKREFN, TESTEN, RXCODE PARAMETER TEST CONDITIONS MIN TYP 1.7 MAX 3.6 UNIT VIH High-level input voltage See Figure 2 VIL Low-level input voltage See Figure 2 0.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com TTL OUTPUT SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = –1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN GND 0.25 tr(slew) Slew rate (rising), magnitude of RX_CLK, RXD[0:19] 0.8 V to 2 V, C = 5 pF, See Figure 3 0.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com DETAILED DESCRIPTION TRANSMIT INTERFACE The TLK2541 offers four modes of operation for the transmit data path. The TLK2541 can operate as a 10 bit SERDES at 10 times the rate of REFCLK or as a 20 bit SERDES at 20 times the rate of REFCLK. At either rate, the data may be serialized exactly as presented on the parallel bus or it may be coded into 8B/10B data codes by way on an integrated 8B/10B encoder.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com When TXRATE is high, the TLK2541 serializes the 20 bit data on TXD[0:19] at a rate of 20 times the reference clock. Bit TXD[0] is the first bit serialized. If the 8B/10B encoders are enabled, then bits TXD[0:7] is encoded into the lower order 10 bit code word and bits TXD[8:15] is encoded into the higher order 10 bit code word. The lower order code word is serialized first. Bit TXD[16] controls whether the lower order code is a Dx.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com Table 3.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com PRBS Generator The TLK2541 has a built-in 27-1 PRBS (pseudo random bit stream) function. When the PRBSEN terminal is forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com in the center of the output data word. The first data bit received is output on RXD[0]. If the 8B/10B encoder is enabled, the data is output as 8 bits of data plus one bit of status. The lower order byte is output on RXD[0:7]. Bit RXD[16] indicates whether the lower order byte was decoded as a Dx.y data word or a Kx.y control word.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is used by the comma detect circuit on the TLK2541 to align the received serial data back to its original byte boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit data.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com Table 5. Receive Status Signals RXD[16] RXD[17] 0 0 Valid data on RXD[0:7], DECODED 20 BIT OUTPUT FULL RATE WITH 8B/10B CODING Valid data RXD[8:15] 0 1 Valid data on RXD[0:7], K code on RXD[8:15] 1 0 K code on RXD[0:7], Valid data on RXD[8:15] 1 1 K code on RXD[0:7], K code on RXD[8:15] RXD[16] DECODED 20 BIT OUTPUT HALF RATE WITH 8B/10B CODING 0 Valid data on RXD[0:7] 1 K code on RXD[0:7] Table 6.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com Reference Clock Input The reference clock (REFCLK) is an external input clock that sets the rate of the transmitted serial data stream. The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock.
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TLK2541 SLLS779B – JANUARY 2008 – REVISED APRIL 2008 www.ti.com APPLICATION INFORMATION Figure 10. External Component Interconnection Figure 11. High-Speed I/O Directly-Coupled Mode Figure 12.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLK2541PFPR Package Package Pins Type Drawing HTQFP PFP 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK2541PFPR HTQFP PFP 80 1000 367.0 367.0 45.
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