TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 D Hot-Plug Protection D 2.5 Gigabits to 3.125 Gigabits Per Second D On-Chip 8-Bit/10-Bit Encoding/Decoding, D High Performance 64-Pin VQFP Thermally D D D (Gbps) Serializer/Deserializer D D Enhanced Package (PowerPAD™) 2.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 description The TLK3101 is a member of the transceiver family of multigigabit transceivers, intended for use in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK3101 supports an effective serial interface speed of 2.5 Gbps to 3.125 Gbps providing up to 2.5 Gbps of data bandwidth. The TLK3101 is functionally identical to the TLK1501, a 0.6 Gbps to 1.5 Gbps transceiver, and the TLK2501, a 1.
TLK3101 2.5 Gbps to 3.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 transmit interface The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of GTX_CLK. The data is then 8-b/10-b encoded, serialized, and transmitted sequentially over the differential high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times creating a bit clock.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 transmit interface (continued) 8-b/10-b encoder All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions in which to stay locked on. The encoding scheme maintains the signal DC balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 transmit interface (continued) high-speed data output The high-speed data output driver consists of a voltage mode differential driver for a 50-Ω impedance environment. The magnitude of the signal swing the differential driver pair is compatible with pseudo emitter coupled logic (PECL) levels when ac-coupled. When ac-coupled the TLK3101 can interface to a PECL transmitter and receiver.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 receive data bus (continued) RX_CLK RXDn, RX_DV, RX_ER tsu th Figure 4. Receive Timing Waveform data reception latency The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is established.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 receive interface (continued) common detect and 8-b/10-b decoding The TLK3101 has two parallel 8-b/10-b decode circuits. Each 8-b/10-b decoder converts 10 bit encoded data (half of the 20 bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte synchronization to an 8-b/10-b transmission code.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 receive interface (continued) power down mode When the ENABLE pin is deasserted low, the TLK3101 will go into a power down mode. In the power down mode, the serial transmit pins (DOUTTXP, DOUTTXN), the receive data bus pins (RXD[0:15]), and RX_ER will go into a high-impedance state. In the power-down mode the RX_DV/LOS pin acts as an output of the signal detection circuit which remains active.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 synchronization and initialization (continued) The state of the transmit data bus, control pins, and serial outputs during the link acquisition process is illustrated in Figure 7. ACQ SYNC TX_EN xx xx xx xx TX_ER xx xx xx xx xx TXD(0−15) xx xx xx xx xx xx xx xx xx xx xx DOUTTXP, DOUTTXN xx xx D0−D15 IDLE D0−D15 Ca. Ext. Error Figure 7.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 redundant port operation The TLK3101 allows users to design redundant ports by connecting receive data bus pins from two TLK3101 devices together. Asserting LCKREFN to a low state will cause the receive data bus pins, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. PRBS verification The TLK3101 also has a built-in BERT function in the receiver side that is enabled by PRBSEN.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 Terminal Functions signal TERMINAL NAME NO. TYPE DESCRIPTION DOUTTXP DOUTTXN 60 59 Output† Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low .
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 Terminal Functions (Continued) signal (continued) TERMINAL NAME NO. TYPE DESCRIPTION PREM 56 Input‡ Preemphasis control. Selects the amount of preemphasis to be added to the high speed data output drivers. Left low or unconnected, 5% of pre-emphasis is added. Pulled high, 20% of preemphasis is added. RX_ER/ PRBS_PASS 29 Output† Receive error.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 Terminal Functions (Continued) power TERMINAL NAME TYPE NO. DESCRIPTION VDD 1, 9, 23, 38, 48 Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers. VDDA 55, 57 Supply Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter GNDA 52, 58, 61 Ground Analog ground.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VDD Supply voltage ICC Supply current PD TEST CONDITIONS MIN TYP MAX 2.3 2.5 2.7 VDD = 2.5V, Freq = 2.5 Gb/sec, PRBS pattern 135 VDD = 2.5V, Freq = 3.125 Gb/sec, PRBS pattern 180 VDD = 2.5V, Freq = 2.5 Gb/sec, PRBS pattern 337 VDD = 2.5V, Freq = 3.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 TTL input electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TTL signals: TXD0 ..TXD15, GTX_CLK, LOOPEN, LCKREFN, PRBS_PASS PARAMETER TEST CONDITIONS VIH High-level input voltage See Figure 10 VIL Low-level input voltage See Figure 10 IIH Input high current VDD = MAX, VIN = 2 V IIL Input low current VDD = MAX, VIN = 0.4 V CI MIN TYP 1.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 TTL output switching characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP VOH High-level output voltage PARAMETER IOH = −1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN GND 0.25 tr(slew) Magnitude of RX_CLK, RX_ER, RX_DV/LOS, RXD slew rate (rising) 0.8 V to 2 V, C = 5 pF, See Figure 11 0.
TLK3101 2.5 Gbps to 3.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 thermal characteristics PARAMETER RθJA RθJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance TEST CONDITION MIN TYP Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 21.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 1 nF − 10 nF† 1 nF − 10 nF† 1 nF − 10 nF† 1 nF − 10 nF† Recommended use of 0.01 µF Capacitor per VDD terminal 0.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 TXP 50 Ω RXP VDDA Transmission Line (See Note A) 50 Ω 4 kΩ 50 Ω 6 kΩ 50 Ω TXN Transmitter Transmission Line Media + _ GND RXN Receiver Note A: Integrated Termination Figure 14. High-Speed I/O Directly-Coupled Mode TXP 50 Ω RXP VDDA (See Note A) Transmission Line 50 Ω 4 kΩ 50 Ω 6 kΩ 50 Ω TXN Transmitter Transmission Line Media + _ GND RXN Receiver Note A: Integrated Termination Figure 15.
TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649B − AUGUST 2000 − REVISED JANUARY 2008 designing with PowerPAD The TLK3101 is housed in a high performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
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