Datasheet

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TLV0834C, TLV0834I, TLV0838C, TLV0838I

3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-Bit Resolution

2.7-V to 3.6-V V

Easy Microprocessor Interface or

Stand-Alone Operation

Operates Ratiometrically or With V

Reference

4- or 8-Channel Multiplexer Options With

Address Logic

Input Range 0 V to V

With V

Reference

Remote Operation With Serial Data Link

Inputs and Outputs Are Compatible With

TTL and MOS

Conversion Time of 32 µs at

(CLK)

= 250 kHz

Functionally Equivalent to the ADC0834

and ADC0838 at 3-V Supply Without the

Internal Zener Regulator Network

Total Unadjusted Error . . . ±1 LSB

description

These devices are 8-bit successive-approximation analog-to-digital converters, each with an input-configurable

multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard

shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is

readily available from the factory.

The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software-configured for single-ended or

differential inputs as well as pseudodifferential input assignments. The differential analog voltage input allows

for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference

input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.

The TLV0834C and TLV0838C are characterized for operation from 0°C to 70°C. The TLV0834I and TLV0838I

are characterized for operation from –40°C to 85°C.

CH0

CH1

CH2

CH3

DGTL GND

CLK

SARS

REF

ANLG GND

TLV0834 ...D OR N PACKAGE

(TOP VIEW)

CH0

CH1

CH2

CH3

DGTL GND

CLK

SARS

REF

ANLG GND

NC – No internal connection

TLV0834 . . . PW PACKAGE

(TOP VIEW)

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DGTL GND

CLK

SARS

REF

ANLG GND

TLV0838 ...PW, DW, OR N PACKAGE

(TOP VIEW)

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(D)

SMALL

OUTLINE

(DW)

PLASTIC DIP

(N)

TSSOP

(PW)

0°C to 70°C TLV0834CD TLV0838CDW TLV0834CN TLV0838CN TLV0834CPW TLV0838CPW

–40°C to 85°C TLV0834ID TLV0838IDW TLV0834IN TLV0838IN TLV0834IPW TLV0838IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (26 pages)

PAGE 1
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 D D D D D D D D 8-Bit Resolution 2.7-V to 3.
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CS CLK CS DI (see Note A) SARS R D S 5-Bit Shift Register R CLK SELECT0 SELECT1 TLC0838 Only SE POST OFFICE BOX 655303 TLC0834 TLC0838 ODD\ EVEN SGL\ DIF START To Internal Circuits CLK • DALLAS, TEXAS 75265 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog MUX S Time Delay EN R CS Comparator CS CS R R CS EN REF Ladder and Decoder SAR Logic and Latch Bits 0–7 One Shot CS CLK Bits 0–7 Bit 1 MSB First NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0
PAGE 3
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 functional description The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing.
PAGE 4
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 sequence of operation TLV0834 1 2 3 4 5 6 10 7 11 12 13 14 15 18 19 20 21 CLK tc CS tsu Start Bit +Sign SELECT Bit Bit 1 SGL ODD Don’t Care DI DIF 1 EVEN Hi-Z SARS MUX Settling Time MSB-First Data DO LSB-First Data Hi-Z Hi-Z MSB 7 LSB 6 2 1 0 MSB 1 2 6 TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS SGL/DIF ODD/EVEN C
PAGE 5
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 sequence of operation (continued) TLV0838 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CLK tc tsu CS MUX Addressing tsu + Sign SEL SEL Start Bit Bit Bit Bit SGL ODD 1 0 Don’t Care DI DIF EVEN 1 0 Hi-Z Hi-Z SARS SE LSB-First Data MSB-First Data Hi-Z DO Hi-Z 7 MSB LSB MSB 6 2 1 0 1 2 3 4 5 6
PAGE 6
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE SELECTED CHANNEL NUMBER MUX ADDRESS SELECT 0 SGL/DIF ODD/EVEN 1 0 CH0 CH1 L L L L + – L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H – 1 CH2 CH3 + – 2 CH4 CH5 + – 3
PAGE 7
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 recommended operating conditions Supply voltage, VCC (see clock frequency operating conditions) High-level input voltage, VIH MIN NOM MAX 2.7 3.3 3.6 2 Clock frequency, f(CLK) VCC = 2.7 V VCC = 3.3 V Clock duty cycle (see Note 2) V V Low-level input voltage, VIL Clock frequency, f(CLK) UNIT 0.
PAGE 8
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 electrical characteristics over recommended range of operating free-air temperature, VCC = 3.
PAGE 9
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 PARAMETER MEASUREMENT INFORMATION VCC CLK 50% 50% GND tsu tsu VCC CS 0.4 V GND th th VCC 2V 2V DI 0.4 V 0.4 V GND Figure 1. Data-Input Timing VCC CLK 50% 50% GND tpd tpd VCC DO 50% 50% GND tsu VCC 50% SE GND Figure 2.
PAGE 10
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 PARAMETER MEASUREMENT INFORMATION VCC Test Point S1 RL From Output Under Test CL (see Note A) S2 LOAD CIRCUIT tr tr VCC CS 50% 90% 10% CS 10% GND S1 open S2 closed VCC 90% DO and SARS S1 closed S2 open GND VOLTAGE WAVEFORMS VCC 10% VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3.
PAGE 11
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS LINEARITY ERROR vs REFERENCE VOLTAGE UNADJUSTED OFFSET ERROR vs REFERENCE VOLTAGE 1.5 VCC = 3.3 V f(CLK) = 250 kHz TA = 25°C VI(+) = VI(–) = 0 V 14 1.25 12 E L – Linearity Error – LSB EO(unadj) – Unadjusted Offset Error – LSB 16 10 8 6 4 1.0 0.75 0.5 0.25 2 0 0.01 0.
PAGE 12
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TLV0831 TLV0831 SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs CLOCK FREQUENCY 0.3 0.5 f(CLK) = 250 kHz CS = High VCC = 3.3 V TA = 25°C 0.4 I CC – Supply Current – mA I CC – Supply Current – mA VCC = 3.6 V VCC = 3.3 V 0.2 VCC = 3 V 0.3 0.2 0.1 0.
PAGE 13
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS 1 0.5 0 Vref = 3.3 V TA = 25°C f(CLK) = 250 kHz VDD = 3.3 V – 0.5 –1 0 32 64 96 128 160 192 224 256 224 256 Output Code Figure 11. Differential Nonlinearity With Output Code Integral Nonlinearity – LSB 1 Vref = 3.3 V TA = 25°C f(CLK) = 250 kHz VDD = 3.3 V 0.5 0 – 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV0834CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV0834CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV0834IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV0834CDR SOIC D 14 2500 367.0 367.0 38.0 TLV0834CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV0834IDR SOIC D 14 2500 367.0 367.0 38.0 TLV0834IPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV0838CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV0838CPWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.