Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal TSSOP 20

 

      

    

SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Maximum Throughput 200-KSPS

D Built-In Reference, Conversion Clock and

8× FIFO

D Differential/Integral Nonlinearity Error:

±1 LSB

D Signal-to-Noise and Distortion Ratio:

59 dB, f

= 12-kHz

D Spurious Free Dynamic Range: 72 dB,

= 12- kHz

D SPI (CPOL = 0, CPHA = 0)/DSP-Compatible

Serial Interfaces With SCLK up to 20-MHz

D Single Wide Range Supply 2.7 Vdc to

5.5 Vdc

D Analog Input Range 0-V to Supply Voltage

With 500 kHz BW

D Hardware Controlled and Programmable

Sampling Period

D Low Operating Current (1.0-mA at 3.3-V,

1.1-mA at 5.5-V With External Ref

D Power Down: Software/Hardware

Power-Down Mode (1 µA Max, Ext Ref),

Autopower-Down Mode (1 µA, Ext Ref)

D Programmable Auto-Channel Sweep

D Pin Compatible 12-Bit Upgrades Available

(TLV2544, TLV2548)

SDO

SDI

SCLK

EOC/(INT

)

REFP

REFM

PWDN

GND

CSTART

TLV1508

DW OR PW PACKAGE

SDO

SDI

SCLK

EOC/(INT

)

REFP

REFM

PWDN

GND

CSTART

(TOP VIEW)

TLV1504

D OR PW PACKAGE

description

The TLV1508 and TLV1504 are a family of high performance, 10-bit low power, 3.86 µs, CMOS analog-to-digital

converters (ADC) which operate from a single 2.7-V to 5.5-V power supply. These devices have three digital

inputs and a 3-state output [chip select (CS

), serial input-output clock (SCLK), serial data input (SDI), and serial

data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors

(SPI interface). When interfaced with a TMS320t DSP, a frame sync (FS) signal is used to indicate the start

of a serial data frame.

In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog

multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold

function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special

pin, CSTART

, to extend the sampling period (extended sampling). The normal sampling period can also be

programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular

among high-performance signal processors. The TLV1508 and TLV1504 are designed to operate with very low

power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down

modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The

converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when

a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional

external reference can also be used to achieve maximum flexibility.

  !"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+

$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '0+ '+$%( #" +1&( !('$*%+!'(

('&!/&$/ 2&$$&!'3 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+

'+('!4 #" &.. ,&$&%+'+$(

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

Summary of content (47 pages)

PAGE 1
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 D Maximum Throughput 200-KSPS D Built-In Reference, Conversion Clock and 8× FIFO D Differential/Integral Nonlinearity Error: D D D D ±1 LSB Signal-to-Noise and Distortion Ratio: 59 dB, fi = 12-kHz Spurious Free Dynamic Range: 72 dB, fi = 12- kHz SPI (CPOL = 0, CPHA = 0)/DSP-Compatible Serial Interfaces With SCLK up to 20-MHz Single Wid
PAGE 2
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 description (continued) The TLV1504I and the TLV1508I are characterized for operation from − 40°C to 85°C.
PAGE 3
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 Terminal Functions TERMINAL NO. I/O DESCRIPTION 6 7 8 9 10 11 12 13 I Analog signal inputs. The analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal to 1 kΩ. 16 20 I Chip select.
PAGE 4
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 Terminal Functions (Continued) TERMINAL NAME SDO NO. TLV1504 TLV1508 1 1 I/O DESCRIPTION O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and after the CS falling edge and until the MSB is presented. The output format is MSB first.
PAGE 5
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 detailed description (continued) Charge Redistribution DAC _ Ain Control Logic + ADC Code REFM Figure 1. Simplified Model of the Successive-Approximation System serial interface INPUT DATA FORMAT MSB LSB D15−D12 D11−D0 Command ID[15:12] Configuration data field ID[11:0] Input data is binary.
PAGE 6
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 control and timing power up and initialization requirements D Determine processor type by writing A000h to the TLV1504/48 (CS must be toggled) D Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e., active FS.
PAGE 7
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 control and timing (continued) configuration Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once configured after first power up, the information is retained in the H/W or S/W power down state.
PAGE 8
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 normal sampling When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input source resistance is high.
PAGE 9
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TLV1504/TLV1508 conversion modes The TLV1504 and TLV1508 have four different conversion modes (mode 00, 01, 10, 11). The operation of each mode is slightly different, depending on how the converter performs the sampling and which host interface is used.
PAGE 10
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TLV1504/TLV1508 conversion modes (continued) Table 4.
PAGE 11
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 timing diagrams The timing diagrams can be categorized into two major groups: nonconversion and conversion. The nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion cycles are those four modes of conversion.
PAGE 12
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 read cycle (read FIFO or read CFR) (continued) FIFO read cycle The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read command. The first FIFO content is output immediately before the command is decoded.
PAGE 13
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 write cycle (write CFR) The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle does not generate an EOC or INT, nor does it carry out any conversion (see power up and initialization requirements).
PAGE 14
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 conversion cycles DSP/normal sampling 1 2 3 4 5 6 7 10 16 − Short Sampling 30 − Short Sampling 28 − Long Sampling 42 − Long Sampling (If CONV CLK = SCLK0 SCLK tc (30 or 42 SCLKs) CS FS SDI INT ÏÏÏ ÏÏÏ ID15 ID14 ID13 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ID12 ID15 t(sample) (12 or 24 SCLKs) ÏÏÏÏÏÏ ÏÏÏÏÏÏ
PAGE 15
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 conversion cycles (continued) Device Going Into Extended Sampling Mode Select/Read Cycle Select/Read Cycle Read Cycle Device Get Out Extended Sampling Mode CS t(sample ) Normal Cycle CSTART ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ FS t(conv) † SDI † INT EOC SDO Previous Conversion Result Previous
PAGE 16
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 modes using the FIFO: modes 01, 10, 11 timing (continued) Conversion #1 From Channel 2 Configure Select CS Conversion #4 From Channel 2 Select ¶ FS (DSP) t(sample) t(sample) t(sample) t(sample) CSTART SDI INT SDO ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏ † § ‡ ‡ ‡ ‡ § Hi-Z Hi-
PAGE 17
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 modes using the FIFO: modes 01, 10, 11 timing (continued) Conversion From Channel 0 Conversion From Channel 3 Conversion From Channel 3 Conversion From Channel 0 Configure CS FS (DSP) CSTART t(sample) t(sample) t(sample) t(sample) SDI INT ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ‡ † ‡ ‡ ‡ #3 #4 ‡
PAGE 18
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 FIFO operation Serial SDO 10-BIT×8 FIFO ADC 7 6 FIFO Full 5 4 3 2 1 0 FIFO 1/2 Full FIFO 3/4 Full FIFO 1/4 Full FIFO Threshold Pointer Figure 15. TLV1504/TLV1508 FIFO The device has an 8-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host after the preprogrammed threshold is reached.
PAGE 19
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 reference block equivalent circuit INT REF Close = Int Ref Used Open = Ext Ref Used REFP Sample 0.1 µF Decoupling Cap 10 µF Internal Reference Compensation Cap Convert ~50 pF CDAC REFM (See Note A) External to the Device NOTES: A. If internal reference is used, tie REFM to analog ground and install a 10-µF (or 4.
PAGE 20
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 21
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 recommended operating conditions (continued) MIN NOM Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV) (See Figure 16) Delay time, delay from SCLK falling edge (FS is active) or SCLK rising edge (FS=1) to SDO valid, td(SCLK-DOV).
PAGE 22
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 electrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to 5.5 V, VREFM = 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCC = 5.5 V, IOH = −0.2 mA at 25-pF load VCC = 2.7 V, IOH = -20 µA at 25-pF load VCC = 5.5 V, IOL = 0.
PAGE 23
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 electrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to 5.
PAGE 24
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 operating characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to 5.
PAGE 25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 INT EOC SDO SDI td(FSL-DOV) tsu(DI-SCLK) 1 ID15 tc(SCLK) twH(SCLK) Hi-Z td(SCLK-DOV) OD8 ID1 twL(SCLK) 15 16 ID0 td(SCLK-CSH) t(conv) td(CSL-INTH) td(SCLK-INTL) td(SCLK-EOCL) Figure 16.
PAGE 26
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 PARAMETER MEASUREMENT INFORMATION SELECT CYCLE VIH CS VIL td(CSH-CSTARTL) twL(CSTART) VIH CSTART † VIL td(CSTARTH-INTL) t(conv) VOH EOC VOL td(CSTARTH-EOCL) td(CSL-INTH) VOH INT VOL † CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE. Figure 17.
PAGE 27
INT EOC SDO SDI Hi-Z td(SCLK-DOV) td(CSL-DOV) ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ SCLK OD9 ID15 1 2 OD0 ID0 16 td(SCLK-INTL) td(SCLK-EOCL) OD1 ID1 twL(SCLK) 15 td(SCLK-CSH) t(conv) Figure 19.
PAGE 28
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs TEMPERATURE INTEGRAL NONLINEARITY vs TEMPERATURE 0.19 0.250 VCC = 5 V, Internal Reference = 4 V, Internal OSC, Single Shot, Short Sample, Mode 00 µP mode DNL − Differential Nonlinearity − LSB INL − Integral Nonlinearity − LSB 0.20 0.18 0.17 0.16 0.15 −40 −15 10 35 60 0.
PAGE 29
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE −0.100 0.650 VCC = 5 V, External Reference = 4 V, External OSC = SCLK/4, Single Shot, Short Sample, Mode 00 µP mode −0.125 Gain Error − LSB Offset Error − LSB 0.625 0.600 −0.150 −0.175 0.575 0.
PAGE 30
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs SAMPLES 0.25 0.20 0.15 0.10 0.05 −0.00 −0.05 −0.10 −0.15 −0.20 −0.25 −0.30 VCC = 2.7 V, Internal Reference = 2 V, SCLK = 12.
PAGE 31
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs SAMPLES 0.20 VCC = 5 V, Internal Reference = 4 V, SCLK = 20 MHz, Internal Conversion OSC, Single Shot, Short Sample, Mode 00 DSP Mode 0.15 0.10 0.05 −0.00 −0.05 −0.10 −0.15 −0.
PAGE 32
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM vs FREQUENCY 20 VCC = 5 V, External Reference = 4 V, SCLK = 20 MHz, Internal OSC Single Shot, Long Sample Mode 00 µP Mode 0 Magnitude − dB −20 −40 −60 −80 −100 −120 −140 0 10 20 30 40 50 60 70 80 f − Frequency − kHz Figure 32 SIGNAL-TO-NOISE vs INPUT FREQUENCY −50 SNR − Signal-
PAGE 33
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 10.0 VCC = 5 V, External Reference = 4 V, Internal OSC, Single Shot, Short Sample, Mode 00 µP Mode ENOB − Effective Number of Bits − BITS SINAD − Signal-to-Noise + Distortion − dB −50 −55 −60 −65 −70 9.5 9.
PAGE 34
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 PRINCIPLES OF OPERATION vcc 10 kΩ VDD XF CS TXD SDI RXD SDO AIN CLKR CLKX TMS320 DSP BIO FSR FSX INT SCLK TLV1504/ TLV1508 FS GND Figure 38. Typical Interface to a TMS320 DSP DATE CODE INFORMATION Parts with a date code earlier than 31xxxxx have the following discrepancies: 1.
PAGE 35
PACKAGE OPTION ADDENDUM www.ti.
PAGE 36
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 37
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV1504IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV1508IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 38
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV1504IPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV1508IPWR TSSOP PW 20 2000 367.0 367.0 38.
PAGE 39
PAGE 40
PAGE 41
PAGE 42
PAGE 43
PAGE 44
PAGE 45
PAGE 46
PAGE 47
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.