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      

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

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D 3.3-V Supply Operation

D 10-Bit-Resolution A/D Converter

D 11 Analog Input Channels

D Three Built-In Self-Test Modes

D Inherent Sample and Hold

D Total Unadjusted Error . . . ±1 LSB Max

D On-Chip System Clock

D End-of-Conversion (EOC) Output

D Pin Compatible With TLC1543

D CMOS Technology

description

The TLV1543C, TLV1543I, and TLV1543M are

CMOS 10-bit, switched-capacitor, successive-

approximation, analog-to-digital converters.

These devices have three inputs and a 3-state

output [chip select (CS

), input-output clock (I/O

CLOCK), address input (ADDRESS), and data

output (DATA OUT)] that provide a direct 4-wire

interface to the serial port of a host processor. The

devices allow high-speed data transfers from the

host.

In addition to a high-speed A/D converter and

versatile control capability, these devices have an

on-chip 14-channel multiplexer that can select

any one of 11 analog inputs or any one of three

internal self-test voltages. The sample-and-hold

function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate

that conversion is complete. The converter incorporated in the devices features differential high-impedance

reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and

supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air

temperature range.

The TLV1543C is characterized for operation from 0°C to 70°C. The TLV1543I is characterized for industrial

temperature range of −40°C to 85°C. The TLV1543M is characterized for operation over the full military

temperature range of −55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DB)

SMALL

OUTLINE

(DW)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

PLASTIC DIP

(N)

PLASTIC CHIP

CARRIER

(FN)

0°C to 70°C TLV1543CDB TLV1543CDW — — TLV1543CN TLV1543CFN

−40°C to 85°C TLV1543IDB — — — — —

−55°C to 125°C — — TLV1543MFK TLV1543MJ — —

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

EOC

I/O CLOCK

ADDRESS

DATA OUT

REF+

REF−

A10

DB, DW, FK, J, OR N PACKAGE

(TOP VIEW)

3212019

910111213

I/O CLOCK

ADDRESS

DATA OUT

REF+

FN PACKAGE

(TOP VIEW)

A10

REF −

EOC

GND

Summary of content (29 pages)

PAGE 1
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 D D D D D D D D D D 3.3-V Supply Operation 10-Bit-Resolution A/D Converter 11 Analog Input Channels Three Built-In Self-Test Modes Inherent Sample and Hold Total Unadjusted Error . . .
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 functional block diagram 1 2 3 4 5 6 7 8 9 11 12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 REF + REF − 14 13 10-Bit Analog-to-Digital Converter (switched capacitors) Sample and Hold 10 14-Channel Analog Multiplexer 4 Output Data Register Input Address Register 10 10-to-1 Data Selector and Driver 16 DATA OUT 4 3 System Clock, Control Logic, and
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 Terminal Functions TERMINAL I/O DESCRIPTION 17 I Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 detailed description (continued) There are six basic serial interface timing modes that can be used with the device. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 Table 2. Analog-Channel-Select Address ANALOG INPUT SELECTED VALUE SHIFTED INTO ADDRESS INPUT BINARY HEX A0 0000 0 A1 0001 1 A2 0010 2 A3 0011 3 A4 0100 4 A5 0101 5 A6 0110 6 A7 0111 7 A8 1000 8 A9 1001 9 A10 1010 A Table 3.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 converter and analog input (continued) SC Threshold Detector 512 Node 512 REF − 256 128 REF+ REF+ REF − REF − ST ST 16 8 REF+ REF − ST 4 REF+ REF − ST REF+ REF − ST 2 1 REF+ REF+ REF − ST REF − ST To Output Latches 1 REF − ST ST VI Figure 1.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 recommended operating conditions Supply voltage, VCC MIN NOM MAX TLV1543C/TLV1543I 3 3.3 5.5 V TLV1543M 3 3.3 3.6 V Positive reference voltage, Vref + (see Note 2) VCC 0 Negative reference voltage, Vref − (see Note 2) Differential reference voltage, Vref + − Vref − (see Note 2) 2.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION Test Point VCC Test Point VCC RL = 2.18 kΩ RL = 2.18 kΩ EOC DATA OUT 12 kΩ CL = 50 pF 12 kΩ CL = 100 pF Figure 2. Load Circuits Address Valid 2V CS tPZH, tPZL DATA OUT 2V VIL ADDRESS VIL tPHZ, tPLZ 2.4 V 90% 0.4 V 10% th(A) tsu(A) I/O CLOCK VIL Figure 3. DATA OUT to Hi-Z Voltage Waveforms Figure 4.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION tt(I/O) tt(I/O) I/O CLOCK 2V 2V VIL VIL VIL I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 0.4 V 2.4 V 0.4 V tr(bus), tf(bus) Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms I/O CLOCK 10th Clock VIL td(I/O-EOC) 2.4 V EOC 0.4 V tf(EOC) Figure 7. I/O CLOCK and EOC Voltage Waveforms tr(EOC) 2.4 V EOC 0.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 8 9 10 Sample Cycle B ÎÎÎÎÎÎ ÎÎÎÎÎÎ 1 Hi-Z State DATA OUT A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Previous Conversion Data MSB B9 ÎÎÎÎ ÎÎÎÎ LSB ADDRESS B3 B2 B1 B0 MSB C3 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previo
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 ÏÏÏ ÏÏÏ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ See Note B CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A9 A8 7 8 9 10 Sample Cycle B A7 A6 A5 A4 A3 A2 A1 A0 Previous Conversion Data ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ MSB 11 Low Level LSB ADDRESS B3 B2 B1 B0 MSB 1 16 Hi-Z B9 C3 LSB EOC Shift in New Multiplexer Address,
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A9 A8 A7 7 8 9 10 Sample Cycle B A6 A5 A4 A3 A2 A1 A0 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ Hi-Z State Low Level LSB ADDRESS B3 B2 B1 B0 MSB 1 16 See Note B Previous Conversion Data MSB 11 ÏÏÏ ÏÏÏ ÎÎÎ ÎÎÎ B9 ÎÎÎÎÎ ÎÎÎÎÎ C3 ÏÏÏ ÏÏÏ LSB EOC Shift in New
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 APPLICATION INFORMATION 1023 1111111111 See Notes A and B 1022 1111111110 1021 1111111101 VF T = VFS − 1/2 LSB 513 1000000001 512 1000000000 VZ T = VZS + 1/2 LSB Step Digital Output Code VFS 511 0111111111 VZS 0000000001 1 0000000000 0 0.0048 0.0096 2.4528 2.4576 4.9056 2.4624 4.9080 2 0.0024 0000000010 4.9104 0 4.
PAGE 17
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by ( VC = VS 1−e −t c /RtCi ) (1) Where: Rt = Rs + ri The final voltage to 1/2 LSB is given by V
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV1543MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TLV1543MJ OBSOLETE CDIP J 20 TBD Call TI Call TI TLV1543MJB OBSOLETE CDIP J 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV1543CDBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 TLV1543CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLV1543IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV1543CDBR SSOP DB 20 2000 367.0 367.0 38.0 TLV1543CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV1543IDBR SSOP DB 20 2000 367.0 367.0 38.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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