Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOIC 8

 

  

 



SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Output Swing Includes Both Supply Rails

D Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz

D Low Input Bias Current ...1 pA Typ

D Fully Specified for Both Single-Supply and

Split-Supply Operation

D Low Power . . . 500 µA Max

D Common-Mode Input Voltage Range

Includes Negative Rail

D Low Input Offset Voltage

950 µV Max at T

= 25°C (TLV226xA)

D Wide Supply Voltage Range

2.7 V to 8 V

D Macromodel Included

D Available in Q-Temp Automotive

HighRel Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The TLV2262 and TLV2264 are dual and quad low

voltage operational amplifiers from Texas Instru-

ments. Both devices exhibit rail-to-rail output

performance for increased dynamic range in

single or split supply applications. The TLV226x

family offers a compromise between the micro-

power TLV225x and the ac performance of the

TLC227x. It has low supply current for battery-

powered applications, while still having adequate

ac performance for applications that demand it.

This family is fully characterized at 3 V and 5 V and

is optimized for low-voltage applications. The

noise performance has been dramatically im-

proved over previous generations of CMOS

amplifiers. Figure 1 depicts the low level of noise

voltage for this CMOS amplifier, which has only

200 µA (typ) of supply current per amplifier.

The TLV226x, exhibiting high input impedance

and low noise, are excellent for small-signal

conditioning for high-impedance sources, such as

piezoelectric transducers. Because of the micro-

power dissipation levels combined with 3-V

operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the

rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with

analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available and has a

maximum input offset voltage of 950 µV.

The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output

dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to

be used in a wider range of applications. For applications that require higher output drive and wider input voltage

range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the

TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their

small size and low power consumption make them ideal for high density, battery-powered equipment.

  !"# $ %!!# $  &%'(# #)

!%#$ !" # $&#$ &! #* #!"$  $ $#!%"#$

$#! +!!#,) !%# &!$$- $ # $$!(, (%

#$#-  (( &!"#!$)



Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinCMOS is a trademark of Texas Instruments.

− High-Level Output Voltage − V

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

| I

| − High-Level Output Current − µA

Figure 1

0.5

0 500 1000

3.5

1500 200

2.5

1.5

= −55°C

= 3 V

= 85°C

= −40°C

= 125°C

= 25°C

 &!%#$ "&(# # ./0.0 (( &!"#!$ ! #$#

%($$ #*!+$ #)  (( #*! &!%#$ &!%#

&!$$- $ # $$!(, (% #$#-  (( &!"#!$)

Summary of content (64 pages)

PAGE 1
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 D D D D D D Output Swing Includes Both Supply Rails Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz Low Input Bias Current . . . 1 pA Typ Fully Specified for Both Single-Supply and Split-Supply Operation Low Power . . . 500 µA Max Common-Mode Input Voltage Range Includes Negative Rail D Low Input Offset Voltage D D D 950 µV Max at TA = 25°C (TLV226xA) Wide Supply Voltage Range 2.
PAGE 2
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262 AVAILABLE OPTIONS PACKAGED DEVICES VIOmax AT 25°C TA SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) CERAMIC FLATPACK (U) 0°C to 70°C 2.5 mV TLV2262CD — — TLV2262CP TLV2262CPWLE — −40°C to 125°C 950 µV 2.5 mV TLV2262AID TLV2262ID — — — — TLV2262AIP TLV2262IP TLV2262AIPWLE — — — −40°C to 125°C 950 µV 2.
PAGE 3
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262C, TLV2262AC TLV2262I, TLV2262AI TLV2262Q, TLV2262AQ D, P, OR PW PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD − /GND 1 8 2 7 3 6 4 5 TLV2264I, TLV2264AI TLV2264Q, TLV2264AQ D, N, OR PW PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD + 2IN + 2IN − 2OUT VDD + 2OUT 2IN − 2IN + TLV2262M, TLV2262AM JG PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD − /GND 1 8 2 7 3 6 4 5 1OUT 1IN − 1IN
PAGE 4
IN − IN + Q1 Q5 R4 Q2 R3 Q3 Q4 equivalent schematic (each amplifier) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q8 Q10 R6 Q9 3 Capacitors 6 18 54 76 TLV2254 † Includes both amplifiers and all ESD, bias, and trim circuitry 9 28 Diodes Resistors TLV2252 38 COMPONENT Transistors R1 Q13 C1 Q12 VDD −/ GND Q11 R5 ACTUAL DEVICE COMPONENT COUNT† Q7 Q6 VDD + R2 Q15 Q14 D1 Q17 Q16 OUT Template Release Date: 7−11−94 1 1 
PAGE 5
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TA† TEST CONDITIONS TLV2262I MIN 25°C MAX 300 2500 Full range Input offset current Common-mode input voltage range RS = 50 Ω Ω, V
PAGE 7
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER IDD Supply current TA† TEST CONDITIONS VO = 1.5 V, No load TLV2262I MIN 25°C TLV2262AI TYP MAX 400 500 Full range MIN TYP MAX 400 500 500 500 UNIT µA † Full range is − 40°C to 125°C.
PAGE 8
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TA† TEST CONDITIONS TLV2262I MIN 25°C 25°C 25 C to 85°C Input offset current Input bias current Common-mode input voltage range |VIO
PAGE 9
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA† TLV2262I MIN 25°C IDD Supply current VO = 2.5 V, No load TLV2262AI TYP MAX 400 500 Full range MIN TYP MAX 400 500 500 500 UNIT µA A † Full range is − 40°C to 125°C.
PAGE 10
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current TA† TEST CONDITIONS TLV2264I MIN 25°C 25°C 25 C to 85°C Input bias current Common-mode input voltage range RS =
PAGE 11
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER Supply current (four amplifiers) IDD TA† TEST CONDITIONS VO = 1.5 V, No load TLV2264I MIN 25°C TLV2264AI TYP MAX 0.8 1 Full range MIN TYP MAX 0.8 1 1 1 UNIT mA † Full range is − 40°C to 125°C.
PAGE 12
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current TA† TEST CONDITIONS TLV2264I MIN 25°C VICR 25°C 25 C to 85°C Input bias current Common-mode input voltage range
PAGE 13
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER Supply current (four amplifiers) IDD TEST CONDITIONS VO = 2.5 V, No load TA† TLV2264I MIN 25°C TLV2264AI TYP MAX 0.8 1 Full range MIN TYP MAX 0.8 1 1 1 UNIT mA † Full range is − 40°C to 125°C.
PAGE 14
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2262Q, TLV2262M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current 25°C Common-mode input voltage r
PAGE 15
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS TLV2262Q, TLV2262M MIN IDD Supply current VO = 1.
PAGE 16
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TLV2262Q, TLV2262M TA† TEST CONDITIONS MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode input voltage r
PAGE 17
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TLV2262Q, TLV2262M TA† MIN IDD Supply current VO = 2.
PAGE 18
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2264Q, TLV2264M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current 25°C Common-mode input voltage r
PAGE 19
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TLV2264Q, TLV2264M TA† MIN Supply current (four amplifiers) IDD VO = 1.5 V, No load 25°C TLV2264AQ, TLV2264AM TYP MAX 0.8 1 Full range MIN UNIT TYP MAX 0.
PAGE 20
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TLV2264Q, TLV2264M TA† TEST CONDITIONS MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode input voltage r
PAGE 21
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TLV2264Q, TLV2264M TA† MIN Supply current (four amplifiers) IDD VO = 2.5 V, No load 25°C TLV2264AQ, TLV2264AM TYP MAX 0.8 1 Full range MIN UNIT TYP MAX 0.
PAGE 22
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution vs Common-mode voltage 2−5 6, 7 αVIO IIB/IIO Input offset voltage temperature coefficient Distribution 8 − 11 Input bias and input offset currents vs Free-air temperature 12 VI Input voltage vs Supply voltage vs Free-air temperature 13 14 VOH VOL High-level output voltage vs High-level outp
PAGE 23
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2262 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLV2262 INPUT OFFSET VOLTAGE 15 12 841 Amplifiers From 2 Wafer Lots VDD± = ± 1.5 V TA = 25°C Precentage of Amplifiers − % Precentage of Amplifiers − % 15 9 6 3 0 −1.6 −0.8 0 0.8 VIO − Input Offset Voltage − mV 12 841 Amplifiers From 2 Wafer Lots VDD± = ± 2.5 V TA = 25°C 9 6 3 0 −1.6 1.
PAGE 24
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE 1 1 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV VDD = 3 V RS = 50 Ω TA = 25°C 0.5 0 ÁÁ ÁÁ ÁÁ ÁÁ −0.5 −1 −1 −0.5 0 0.5 1 1.5 2 2.5 VDD = 5 V RS = 50 Ω TA = 25°C 0.5 0 −0.
PAGE 25
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2264 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT DISTRIBUTION OF TLV2264 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 35 128 Amplifiers From 2 Wafer Lots 30 VDD± = ± 1.5 V N Package TA = 25°C to 125°C 25 128 Amplifiers From 2 Wafer Lots VDD ± = ± 2.
PAGE 26
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT VOLTAGE†‡ vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT 5 4 VDD = 5 V VDD = 3 V 3.5 VOH − High-Level Output Voltage − V 4 VI − Input Voltage − V 3 | VIO | ≤ 5 mV 2 ÁÁ 1 0 −1 −55 −35 −15 5 25 45 65 85 105 125 TA − Free-Air Temperature − °C ÁÁ ÁÁ ÁÁ 3 TA = − 55°C 2.5 TA = 125°C 2 TA = 25°C 1.
PAGE 27
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE†‡ vs LOW-LEVEL OUTPUT CURRENT 6 1.4 VDD = 5 V VIC = 2.5 V ÁÁ ÁÁ 1.2 5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VDD = 5 V TA = − 55°C 4 TA = − 40°C 3 TA = 25°C TA = 125°C 2 TA = 85°C 0 500 TA = 85°C 0.8 TA = 25°C 0.
PAGE 28
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS SHORT-CIRCUIT OUTPUT CURRENT † vs FREE-AIR TEMPERATURE DIFFERENTIAL INPUT VOLTAGE‡ vs OUTPUT VOLTAGE 1000 VO = 2.5 V VDD = 5 V 10 VID = − 100 mV 8 6 4 2 0 VID = 100 mV −2 −4 −75 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VDD = 3 V RI = 50 kΩ VIC = 1.
PAGE 29
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN† vs FREQUENCY 60 AVD A VD − Large-Signal Differential Voltage Amplification − dB 180° VDD = 5 V CL= 100 pF TA = 25°C 135° 40 Phase Margin 20 ÁÁ ÁÁ ÁÁ 90° 45° Gain 0 0° −20 φom m − Phase Margin 80 −45° −40 103 104 105 −90° 107 106 f − Frequency − Hz Figure 26 LARGE-SIGNAL DIFFERENT
PAGE 30
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION†‡ vs FREE-AIR TEMPERATURE LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION†‡ vs FREE-AIR TEMPERATURE 1000 10000 VDD = 5 V VIC = 2.
PAGE 31
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO† vs FREQUENCY COMMON-MODE REJECTION RATIO†‡ vs FREE-AIR TEMPERATURE 90 VDD = 5 V VIC = 2.5 V CMMR − Common-Mode Rejection Ratio − dB CMRR − Common-Mode Rejection Ratio − dB 100 TA = 25°C 80 VDD = 5 V VIC = 1.
PAGE 32
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS TLV2262 SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE 110 VDD = 2.7 V to 8 V VIC = VO = VDD / 2 k SVR − Supply-Voltage Rejection Ratio − dB k SVR − Supply-Voltage Rejection Ratio − dB 110 TLV2264 SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE 105 100 ÁÁ ÁÁ 95 90 −75 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VDD = 2.
PAGE 33
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS SLEW RATE†‡ vs FREE-AIR TEMPERATURE SLEW RATE† vs LOAD CAPACITANCE 1 1.2 SR − 1 SR − SR − Slew Rate − V/ µ s SR − Slew Rate − V/ µ s 0.8 0.6 SR + 0.4 0.2 SR + 0.6 0.4 0.2 VDD = 5 V AV = −1 TA = 25°C 0 10 1 0.
PAGE 34
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE† VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE† 3 5 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = −1 TA = 25°C 4 VO − Output Voltage − V VO − Output Voltage − V 2.5 2 1.5 1 3 2 1 0.
PAGE 35
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE† VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE† 0.95 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 2.6 VO VO − Output Voltage − V 0.9 VO VO − Output Voltage − V 2.65 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 0.85 0.8 0.75 2.55 2.5 2.45 0.7 0 2 4 6 8 10 12 t − Time − µs 14 16 18 2.
PAGE 36
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INTEGRATED NOISE VOLTAGE vs FREQUENCY INPUT NOISE VOLTAGE OVER A 10-SECOND PERIOD† 100 1000 Calculated Using Ideal Pass-Band Filter Lower Frequency = 1 Hz TA = 25°C Integrated Noise Voltage − µ V Input Noise Voltage − nV 750 500 250 0 −250 −500 −750 −1000 0 VDD = 5 V f = 0.1 Hz to 10 Hz TA = 25°C 2 10 1 0.
PAGE 37
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE GAIN-BANDWIDTH PRODUCT †‡ vs FREE-AIR TEMPERATURE 75° 1200 TA = 25°C 60° Rnull = 100 Ω 1000 φom m − Phase Margin Gain-Bandwidth Product − kHz VDD = 5 V f = 10 kHz CL = 100 pF 800 Rnull = 50 Ω 45° Rnull = 20 Ω 30° Rnull = 10 Ω 50 kΩ 600 15° 50 kΩ VI 400 −75 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 56
PAGE 38
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS OVERESTIMATION OF PHASE MARGIN† vs LOAD CAPACITANCE 14° TA = 25°C Overestimation of Phase Margin 12° Rnull = 100 Ω 10° 8° Rnull = 50 Ω 6° 4° Rnull = 10 Ω Rnull = 20 Ω 2° 0 10 10 2 10 3 CL − Load Capacitance − pF † See application information Figure 60 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 4
PAGE 39
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION driving large capacitive loads The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51 and Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase margins (Rnull = 0).
PAGE 40
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION driving large capacitive loads (continued) ȱ ȧ Ȳ ǒ ȳ ȧ ȴ Ǔ ∆θ m2 + tan –1 UGBW – tan –1 UGBW P2 ǒF × P2Ǔ Where : ∆θ m2 + reduction in phase margin (3) UGBW + unity-gain bandwidth frequency F + factor from equation (2) P 2 + unadjusted pole (70 MHz @ 10 pF, 7 MHz @ 100 pF, etc.
PAGE 41
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using the TLV226x typical electrical and operating characteristics at TA = 25°C.
PAGE 42
PACKAGE OPTION ADDENDUM www.ti.
PAGE 43
PACKAGE OPTION ADDENDUM www.ti.
PAGE 44
PACKAGE OPTION ADDENDUM www.ti.
PAGE 45
PACKAGE OPTION ADDENDUM www.ti.
PAGE 46
PACKAGE OPTION ADDENDUM www.ti.
PAGE 47
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.
PAGE 48
PACKAGE OPTION ADDENDUM www.ti.
PAGE 49
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2262AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2262AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2262IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 50
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2262AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2262AIPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2262IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2264AIDR SOIC D 14 2500 333.2 345.9 28.6 TLV2264AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2264IDR SOIC D 14 2500 333.2 345.9 28.
PAGE 51
MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
PAGE 52
PAGE 53
PAGE 54
PAGE 55
PAGE 56
PAGE 57
PAGE 58
PAGE 59
PAGE 60
PAGE 61
PAGE 62
PAGE 63
PAGE 64
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.