Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 8

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

D Maximum Throughput . . . 140/200 KSPS

D Built-In Conversion Clock

D INL/DNL: ±1 LSB Max, SINAD: 72 dB,

SFDR: 85 dB, f

= 20 kHz

D SPI/DSP-Compatible Serial Interface

D Single Supply: 2.7 Vdc to 5.5 Vdc

D Rail-to-Rail Analog Input With 500 kHz BW

D Three Options Available:

− TLV2541: Single Channel Input

− TLV2542: Dual Channels With

Autosweep

− TLV2545: Single Channel With

Pseudo-Differential Input

D Low Power With Autopower Down

− Operating Current: 1 mA at 2.7 V, 1.5 mA

at 5 V

Autopower Down: 2 μA at 2.7 V, 5 μA

at 5 V

D Small 8-Pin MSOP and SOIC Packages

TOP VIEW

TLV2541

REF

GND

AIN

SDO

SCLK

REF

GND

AIN0

SDO

SCLK

AIN1

REF

GND

AIN(+)

SDO

SCLK

AIN(−)

TOP VIEW

TLV2542

TOP VIEW

TLV2545

description

The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS

analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices

are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS

), serial

clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most

popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS)

can be used to indicate the start of a serial data frame on CS

for all devices or FS for the TLV2541.

TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving

feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link

to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the

mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock,

providing a 3.5-μs conversion time.

AVAILABLE OPTIONS

PACKAGED DEVICES

8-MSOP

(DGK)

8-SOIC

(D)

TLV2541CDGK (AGZ)

0°C to 70°C

TLV2542CDGK (AHB)

0 C to 70 C

TLV2545CDGK (AHD)

TLV2541IDGK (AHA) TLV2541ID

−40°C to 85°C

TLV2542IDGK (AHC) TLV2542ID

40 C to 85 C

TLV2545IDGK (AHE) TLV2545ID

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

Summary of content (32 pages)

PAGE 1
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 D Maximum Throughput . . . 140/200 KSPS D Built-In Conversion Clock D INL/DNL: ±1 LSB Max, SINAD: 72 dB, D D D D SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.
PAGE 2
TLV2541, TLV2542, TLV2545 2.7-V TO 5.
PAGE 3
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 Terminal Functions TLV2541 TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time. CS can be used as the FS pin when a dedicated DSP serial port is used. FS 7 I DSP frame sync input.
PAGE 4
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 detailed description (continued) Charge Redistribution DAC _ AIN Control Logic + ADC Code GND/AIN(−) Figure 1. Simplified SAR Circuit serial interface OUTPUT DATA FORMAT MSB LSB D15−D4 D3−D0 Conversion result (OD11−OD0) Don’t care The output data format is binary (unipolar straight binary).
PAGE 5
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 control and timing (continued) D Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output data changes on the rising edge of SCLK.
PAGE 6
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 timing diagrams/conversion cycles (continued) 1 2 3 4 5 6 12 13 14 15 16 1 SCLK CS FS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 t(powerdown) tc OD0 Figure 3.
PAGE 7
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 using CS as the FS input (continued) SCLK and conversion speed The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator clocks to complete. This leads to a 3.5-μs conversion time.
PAGE 8
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 ICC VDD = 5 V With 1-μF/0.1-μF Capacitor Between Supply and Ground VDD = 2.7 V 0.5 μS 2 mS 1.5 mA 0.95 mA 5 μA 2 μA 1 μA 1 μA t(Powerdown) − Powerdown time − S Table 1. Modes of Operation and Data Throughput MAX SCLK (MHz) (50/50 duty cycle) CONTROL PIN(s)/DEVICE APPROXIMATE CONVERSION THROUGHPUT (ksps) VDD = 2.
PAGE 9
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 recommended operating conditions Supply voltage, VDD MIN NOM MAX 2.7 3.3 5.5 UNIT V Positive external reference voltage input, VREFP (see Note 1) 2 VDD V Analog input voltage (see Note 1) 0 VDD V High level control input voltage, VIH 2.1 V Low-level control input voltage, VIL 0.
PAGE 10
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 electrical characteristics over recommended operating free-air temperature range, VDD = VREF = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5.5 V, IOH = −0.
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TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 ac specifications (fi = 20 kHz) PARAMETER SINAD Signal to noise ratio +distortion Signal-to-noise THD Total harmonic distortion ENOB Effective number of bits SFDR Spurious free dynamic range TEST CONDITIONS MIN TYP 200 KSPS, VDD = VREF = 5.5 V 70 72 150 KSPS, VDD = VREF = 2.
PAGE 12
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION t(sample) tc tw(H_SCLK) VIH 1 2 4 12 16 SCLK VIL tw(L_SCLK) tsu(CSL-SCLKL) t(powerdown) CS th(SCLKL-FSL) tw(H_CS) tsu(FSH-SCLKL) th(EOC-CSH) td(CSL-FSH) td(SCLKH-SDOV) FS SDO ÎÎÎÎÎ ÎÎÎÎÎ tw(H_FS) OD11 OD8 OD0 td(CSL-SDOV) ÎÎÎÎÎ ÎÎÎÎÎ td(SCLK17H-SDOZ) Figure 6.
PAGE 13
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION t(sample) tc 1 1 4 12 16 SCLK t(reset cycle) MUX = AIN0 CS tw(H_CS) ÎÎÎÎ ÎÎÎÎ SDO th(EOC-CSH) td(SCLKH-SDOV) td(CSL-SDOV) OD11 OD0 td(CSL-SDOV) ÎÎÎÎÎ ÎÎÎÎÎ OD11 td(SCLK17H-SDOZ) Figure 8.
PAGE 14
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.7 0.6 VDD = REF = 5.5 V 200 KSPS INL − Integral Nonlinearity − LSB INL − Integral Nonlinearity − LSB VDD = REF = 2.7 V 150 KSPS 0.65 0.6 −40 0.5 −40 90 25 0.
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TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.5 0.9 VDD = REF = 2.7 V 150 KSPS VDD = REF = 5.5 V 200 KSPS Gain Error − LSB 0.3 0.2 0.85 0.1 0 −40 0.
PAGE 16
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 2.7 V 150 KSPS 0.5 0 −0.5 −1 4095 1 Digital Output Codes Figure 17 DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 2.7 V 150 KSPS 0.5 0 −0.
PAGE 17
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 5.5 V 200 KSPS 0.5 0 −0.5 −1 4095 1 Digital Output Codes Figure 19 DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 5.5 V 200 KSPS 0.5 0 −0.
PAGE 18
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS 2048 POINTS FAST FOURIER TRANSFORM (FFT) 0 VDD = REF = 2.7 V 150 KSPS fi = 20 kHz Magnitude − dB −20 −40 −60 −80 −100 −120 −140 0 20 40 60 80 100 f − Input Frequency − KHz Figure 21 2048 POINTS FAST FOURIER TRANSFORM (FFT) 0 VDD = REF = 5.
PAGE 19
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 75 VDD = REF = 2.7 V 150 KSPS SINAD − Signal-To-Noise + Distortion − dB SINAD − Signal-To-Noise + Distortion − dB 75 73 71 69 67 65 0 10 20 30 40 50 60 70 VDD = REF = 5.
PAGE 20
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY THD − Total Harmonic Distortion − dB −75 VDD = REF = 2.
PAGE 21
TLV2541, TLV2542, TLV2545 2.7-V TO 5.
PAGE 22
TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 APPLICATION INFORMATION VDD TMS320 EXT Reference 10 kΩ 10 kΩ FSX CS SDO SCLK FSR DR CLKR DSP CLKX VDD VREF TLV2542/45 AIN 0/AIN (+)† † GND For TLV2545 only Figure 30.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2541CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2541IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2541CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2541IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2541IDR SOIC D 8 2500 367.0 367.0 35.0 TLV2542CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2542IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2542IDR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.