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TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

12-BIT, 200-KSPS, 11-CHANNEL, LOW-POWER, SERIAL ADC

www.ti.com

FEATURES

12-Bit-Resolution A/D Converter

Up to 200 KSPS (150 KSPS for 3 V)

Throughput Over Operating Temperature

Range With 12-Bit Output Mode

11 Analog Input Channels

3 Built-In Self-Test Modes

Inherent Sample and Hold Function

Linearity Error ...±1 LSB Max

On-Chip Conversion Clock

Unipolar or Bipolar Output Operation

Programmable MSB or LSB First

Programmable Power Down

Programmable Output Data Length

SPI Compatible Serial Interface With I/O Clock

Frequencies up to 15 MHz (CPOL=0, CPHA=0)

APPLICATIONS

Process Control

Portable Data Logging

Battery-Powered Instruments

Automotive

DESCRIPTION

The TLV2553 is a 12-bit, switched-capacitor,

successive-approximation, analog-to-digital converter.

The ADC has three control inputs [chip select (CS

), the

input-output clock, and the address/control input

(DATAIN)], designed for communication with the serial

port of a host processor or peripheral through a serial

3-state output.

In addition to the high-speed converter and versatile

control capability, the device has an on-chip 14-channel

multiplexer that can select any one of 11 inputs or any

one of three internal self-test voltages using

configuration register 1. The sample-and-hold function

is automatic. At the end of conversion, when

programmed as EOC, the pin 19 output goes high to

indicate that conversion is complete. The converter

incorporated in the device features differential, high-

impedance reference inputs that facilitate ratiometric

conversion, scaling, and isolation of analog circuitry

from logic and supply noise. A switched-capacitor

design allows low-error conversion over the full

operating temperature range.

The TLV2553I is characterized for operation from

= –40°C to 85°C. See available options table for

package options.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

GND

EOC

I/O CLOCK

DATA IN

DATA OUT

REF+

REF–

AIN10

AIN9

(TOP VIEW)

DW AND PW PACKAGE

Summary of content (29 pages)

PAGE 1
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 12-BIT, 200-KSPS, 11-CHANNEL, LOW-POWER, SERIAL ADC FEATURES D D D D D D D D D D D D 12-Bit-Resolution A/D Converter Up to 200 KSPS (150 KSPS for 3 V) Throughput Over Operating Temperature Range With 12-Bit Output Mode 11 Analog Input Channels 3 Built-In Self-Test Modes Inherent Sample and Hold Function Linearity Error . . .
PAGE 2
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 AVAILABLE OPTIONS PACKAGE SMALL OUTLINE TA 20-TSSOP (PW) 20-SOWB (DW) TLV2553IPW TLV2553IDW – 40°C to 85°C functional block diagram VCC 20 REF + 14 REF – 13 3 AIN0 1 AIN1 2 AIN2 3 AIN3 4 AIN4 5 AIN5 6 AIN6 7 AIN7 8 AIN8 9 AIN9 11 AIN10 12 Self Test 14-Channel Analog Multiplexer Low Power 12-Bit SAR ADC Sample and Hold 4 Reference CTRL Input Address Register 19 12 Output Data Register 12 12-to-1 Data Selector and Driver DATA IN C
PAGE 3
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AIN0 – AIN10 1 – 9, 11, 12 I Analog input. These 11 analog-signal inputs are internally multiplexed. CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time. DATA IN 17 I Serial data input.
PAGE 4
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . .
PAGE 5
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, VREF+ = 5 V, I/O CLOCK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS High level output voltage High-level Low level output voltage Low-level MIN TYP† MAX VCC = 4.5 V, IOH = –1.6 mA VCC = 2.7 V, IOH = –0.2 mA 30 pF 2.4 VCC = 4.
PAGE 6
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 external reference specifications MIN TYP† MAX voltage REF– REF Reference input voltage, VCC = 4.5 V to 5.5 V VCC = 2.7 V to 3.6 V –0.1 0 0.1 –0.1 0 0.1 Reference input voltage, voltage REF+ VCC = 4.5 V to 5.5 V VCC = 2.7 V to 3.6 V 2 External reference input voltage g difference,, (REF+) – (REF–) VCC = 4.5 V to 5.5 V VCC = 2.7 V to 3.6 V 1.9 External reference supply current CS at 0 V PARAMETER TEST CONDITIONS 2 1.9 VCC = 4.
PAGE 7
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 timing characteristics over recommended operating free-air temperature range, VREF+ = 5 V, I/O CLOCK frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless otherwise noted) PARAMETER MIN tw1 tsu1 Pulse duration I/O CLOCK high or low 26.
PAGE 8
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 timing characteristics over recommended operating free-air temperature range, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz, VCC = 2.
PAGE 9
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE I CC – Supply Current – mA 0.620 0.615 0.43 VCC = 3.3 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz 0.42 External Reference Current – mA 0.625 EXTERNAL REFERENCE CURRENT vs FREE-AIR TEMPERATURE 0.610 0.605 0.600 0.595 0.590 0.585 0.58 –40 0.41 VCC = 3.3 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz 0.40 0.39 0.38 0.37 0.36 0.35 0.34 –25 –10 5 20 35 50 65 0.
PAGE 10
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS MAXIMUM DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.9 0.8 –0.0 VCC = 2.7 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –40 –25 –10 5 20 –0.1 Minimum Differential Nonlinearity – LSB Maximum Differential Nonlinearity – LSB 1.0 MINIMUM DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 35 50 65 VCC = 2.7 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz –0.2 –0.3 –0.4 –0.
PAGE 11
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.5 VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 1024 2048 3072 4096 Digital Output Code Figure 9 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.8 VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C 0.
PAGE 12
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS GAIN ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs FREE-AIR TEMPERATURE 1.4 0.6 1.2 EG – Gain Error – mV EO – Offset Error – mV 0.5 0.4 0.3 0.2 1.0 0.8 0.6 0.4 0.1 0.0 –40 VCC = 3.3 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz –25 –10 5 20 0.2 35 50 65 0.0 –40 80 VCC = 3.3 V VREF+ = 2.5 V VREF– = 0 V I/O CLOCK = 10 MHz –25 –10 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 65 80 0.
PAGE 13
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SOFTWARE POWER DOWN vs FREE-AIR TEMPERATURE AUTO POWER DOWN vs FREE-AIR TEMPERATURE 0.14 0.45 VCC = 5.5 V VREF+ = 4.096 V VREF– = 0 V I/O CLOCK = 15 MHz 0.40 0.35 0.12 Current – µ A Current – µ A 0.10 0.30 0.25 0.20 0.08 0.06 0.15 0.04 VCC = 5.5 V VREF+ = 4.096 V VREF– = 0 V I/O CLOCK = 15 MHz 0.10 0.02 0.05 0.
PAGE 14
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS MAXIMUM INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE MINIMUM INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.90 –0.329 0.86 Minimum Integral Nonlinearity – LSB Maximum Integral Nonlinearity – LSB –0.330 VCC = 5.5 V VREF+ = 4.096 V VREF– = 0 V I/O CLOCK = 15 MHz 0.88 0.84 0.82 0.80 0.78 0.76 0.74 –40 –25 –10 5 20 35 50 65 –0.331 VCC = 5.5 V VREF+ = 4.096 V VREF– = 0 V I/O CLOCK = 15 MHz –0.332 –0.333 –0.
PAGE 15
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.8 0.6 0.4 0.2 –0.0 –0.2 –0.4 –0.6 VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C –0.8 0 1024 2048 3072 4096 Digital Output Code Figure 22 OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE –0.0 –0.00 EO – Offset Error – mV –0.10 VCC = 5.5 V VREF+ = 4.
PAGE 16
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION Data Valid VIH VIL CS td1 VIH VIL DATA IN th1 td2 VOH VOL Data Out I/O CLOCK Figure 25. DATA OUT to Hi-Z Voltage Waveforms th2 VIH VIL Figure 26. DATA IN and I/O CLOCK Voltage tt1 tt1 VIH VIL CS tsu1 VIH VIL I/O CLOCK I/O CLK Period th3 tsu2 I/O CLOCK td3 VIH VIL Last Clock th4 VOH VOL Data Out tt2 Figure 27. CS and I/O CLOCK Voltage Waveforms I/O CLOCK Figure 28.
PAGE 17
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION timing diagrams Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Result CS Access Cycle 1 3 2 Sample Cycle 4 I/O CLOCK 5 6 7 8 9 10 11 12 Previous Conversion Data DATA OUT MSB ÎÎÎ DATA IN D7 D6 Output Data Format D5 D4 D3 D2 D1 LSB MSB MSB–1 MSB–2 ÎÎÎÎÎÎÎÎÎÎÎÎ D0 3 2 Hi–Z State MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1 Channel Addre
PAGE 18
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION timing diagrams (continued) Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Result CS Access Cycle 1 2 3 Sample Cycle 4 5 7 6 8 1 2 3 4 5 6 7 I/O CLOCK Previous Conversion Data Hi–Z State DATA OUT MSB Channel Address ÎÎÎÎ D7 DATA IN MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 D6 D5 LSB+1 LSB Output Data Format D4 D3 D2 MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB ÎÎÎÎÎÎÎ
PAGE 19
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION timing diagrams (continued) Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Result CS Access Cycle 1 Sample Cycle 3 2 4 I/O CLOCK 5 6 7 8 9 10 11 12 Pad Zeros Previous Conversion Data DATA OUT MSB ÎÎÎÎ DATA IN MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 Channel Address D7 D6 Output Data Format D5 D4 D3 D2 D1 D0 16 LSB+1 1 Hi–Z State LSB MS
PAGE 20
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION detailed description Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and removes DATA OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit address or command (D7–D4) and a 4-bit configuration data (D3–D0).
PAGE 21
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION conversion cycle A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to start the OSC.
PAGE 22
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION Table 2.
PAGE 23
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION data output length (continued) With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream during the next I/O cycle.
PAGE 24
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION Analog Supply VCC REF+ Sample C1 0.1 µF Decoupling Cap Convert ∼50 pF CDAC REF– GND Figure 39. Reference Block EOC output Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning and the end of conversion. In the reset state, EOC is always high.
PAGE 25
TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 PRINCIPLES OF OPERATION chip-select input (CS) (continued) CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and shifted out during the next I/O cycle.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2553IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 TLV2553IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2553IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV2553IPWR TSSOP PW 20 2000 367.0 367.0 38.
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