Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTLV320AIC14IDBT

www.ti.com

FEATURES

APPLICATIONS

TLV320AIC12, TLV320AIC13

TLV320AIC14, TLV320AIC15

TLV320AIC12K, TLV320AIC14K

SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007

LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE

16-Bit, 26-KSPS MONO CODEC

– Analog and Digital Sidetone

• Mono 16-Bit Oversampling Sigma-Delta A/D – Antialiasing Filter (AAF)

Converter

– Programmable Input and Output Gain

• Mono 16-Bit Oversampling Sigma-Delta D/A Control (PGA)

Converter

– Microphone/Handset/Headset Amplifiers

• Support Maximum Master Clock of 100 MHz to

– AIC12K has an 8- Ω Speaker Driver

Allow the DSP Output Clock to be Used as a

– Power Management With

Master Clock

Hardware/Software Power-Down Modes

• Selectable FIR/IIR Filter With Bypassing

30 µW

Option

• Separate Software Control for ADC and DAC

• Programmable Sampling Rate up to:

Power Down

– Max 26 Ksps With On-Chip IIR/FIR Filter

• Fully Compatible With Common TMS320™

– Max 104 Ksps With IIR/FIR Bypassed DSP Family and Microcontroller Power

Supplies

• On-Chip FIR Produced 84-dB SNR for ADC

and 92-dB SNR for DAC – 1.65 V - 1.95 V Digital Core Power

• Smart Time Division Multiplexed – 1.1 V - 3.6 V Digital I/O

( SMARTDM™) Serial Port

– 2.7 V - 3.6 V Analog

– Glueless 4-Wire Interface to DSP

• Power Dissipation (P

)

– Automatic Cascade Detection (ACD)

– 11.2 mW at 3.3 V in Standard Operation

Self-Generates Master/Slave Device

– 17.8 mW at 3.3 V With Headphone Drivers

Addresses

• Internal Reference Voltage (V

ref

)

– Programming Mode to Allow On-the-Fly

• 2s Complement Data Format

Reconfiguration

• Test Modes Which Include Digital Loopback

– Continuous Data Transfer Mode to

and Analog Loopback

Minimize Bit Clock Speed

– Support Different Sampling Rate for Each

Device

• Digital Still Cameras

– Turbo Mode to Maximize Bit Clock for

• Wireless Accessories

Faster Data Transfer and Allow Multiple

• Hands-Free Car Kits

Serial Devices to Share the Same Bus

• VOIP

– Allows up to 16 Devices to be Connected

• Cable Modem

to a Single Serial Port

• Host Port

– 2-Wire Interface

– Selectable I

C or S

• Differential and Single-Ended Analog

Input/Output

• Built-In Analog Functions:

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SMARTDM, TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.

TMS320 is a trademark of Texas Instrument.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (64 pages)

PAGE 1
TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TLV320AIC1x is a true low-cost, low-power, high-integrated, high-performance, mono voice codec.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Terminal Functions TERMINAL NAME 4 AIC12/13/12K DBT NO. AIC14/15/14K DBT NO. AIC12K RHB NO. AIC14K RHB NO. I/O IOVSS 1 1 5 5 I Digital I/O ground IOVDD 2 2 6 6 I Digital I/O power supply DESCRIPTION FSD 3 3 7 7 O Frame sync delayed output. The FSD output synchronizes a slave device to the frame sync of the master device.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Terminal Functions (continued) TERMINAL NAME AIC12/13/12K DBT NO. AIC14/15/14K DBT NO. AIC12K RHB NO. AIC14K RHB NO. I/O DESCRIPTION Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Recommended Operating Conditions MIN NOM MAX MIN AIC12/13/14/15 VSS VI(analog) Supply voltage for analog, AVDD 2.7 Supply voltage for analog output driver, DRVDD 2.7 CL 3.6 2.7 3.6 2.7 3.3 3.6 V 3.6 1.65 1.8 1.95 1.65 1.8 1.95 V 1.1 3.3 3.6 1.1 3.3 3.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Digital Inputs and Outputs Fs = 8 kHz, Outputs Not Loaded PARAMETER (1) MIN TYP MAX High-level output voltage, DOUT VOL Low-level output voltage, DOUT IIH High-level input current, any digital input 0.5 µA IIL Low-level input current, any digital input 0.5 µA CI Input capacitance 3 pF Co Output capacitance 5 pF (1) 0.8 IOVDD UNIT VOH V 0.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 DAC Path Filter Fs = 8 KHz (1) (2) TEST CONDITIONS PARAMETER MIN TYP MAX MIN FIR FILTER (2) MAX UNIT IIR FILTER 0 Hz to 30 Hz -0.5 0.2 -0.5 0.2 300 Hz to 3 Hz -0.25 0.25 -0.25 0.35 3.3 Hz -0.35 0.3 -0.75 0.3 Filter gain relative to gain at 1020 Hz (1) TYP 3.6 KHz -3 -3 4 kHz -40 -20 ≥ 4.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 DAC Channel Characteristics PARAMETER TEST CONDITIONS Dynamic range MIN VI = 0 dB at 1020 Hz Interchannel isolation EG Gain error, 0 dB VO = 0 dB at 1020 Hz Common mode voltage TYP 92 dB dB 0.5 dB 1.35 0 kHz-4 kHz (1) 80 VOO Output offset voltage at OUT (differential) DIN = All zeros 10 VO Analog output voltage, (3.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Definitions and Terminology Term Definition Data Transfer Interval The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks and the data transfer is initiated by the falling edge of the FS signal in standard and continuous mode.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Timing Requirements twH 2.4 V MCLK 2.4 V twL tsu1 th1 2.4 V RESET Figure 1. Hardware Reset Timing SCLK td1 td2 td2 td1 FS FSD td3 ten DOUT tdis D15 tsu2 th2 DIN D15 Figure 2.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 SDA tf tLOW tSU;OAT tr tf tHD;STA tBUF tr SCL tHD;STA tHD;DAT tSU;STA tHIGH tSU;STO Figure 3. I2C / S2C Timing TEST CONDITIONS MIN MAX UNIT 0 900 kHz tSCL SCL clock frequency tHD;STA Hold time (repeated START condition. After this period, the first clock pulse is generated.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Parameter Measurement Information (continued) Amplitude - dB 0 -20 Sampling Rate at 8 kHz -40 -60 -80 -100 -120 -140 -160 0 500 1000 1500 2000 2500 f - Frequency - Hz 3000 3500 4000 Figure 5.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Parameter Measurement Information (continued) 0 ADC at 8 kHz Fs = 32 kHz Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 2000 4000 6000 8000 10000 f - Frequency - Hz 12000 14000 16000 Figure 8.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS ADC FILTER GAIN vs FREQUENCY RESPONSE (FIR) ADC FILTER GAIN vs FREQUENCY RESPONSE (IIR) 5 5 0 0 −5 −10 Filter Gain − dB Filter Gain − dB −5 −10 −15 −15 −20 −25 −30 −20 −35 −25 −40 −30 −45 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 f − Frequency − Hz Figure 10. Figure 11.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) DAC FILTER GAIN vs FREQUENCY (FIR/IIR BYPASS) 4 4 2 2 0 0 -2 -2 Filter Gain - dB Filter Gain - dB ADC FILTER GAIN vs FREQUENCY (FIR/IIR BYPASS) -4 -6 -8 -4 -6 -8 -10 -10 -12 -12 -14 -14 0 2000 4000 6000 8000 10 k 12 k 14 k 16 k 0 2000 4000 6000 8000 10 k f - Frequency - Hz Figure 14. Figure 15.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Functional Description (continued) Decimation Filter The decimation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter provides linear-phase output with 17/fs group delay, whereas the IIR filter generates nonlinear phase output with negligible group delay.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Functional Description (continued) MIC Input TLV320AIC1x supports single ended microphone input. This can be used by connecting the external single ended source through ac coupling to the MICIN pin. This channel is selected by writing 01 or 10 into bits D2-D1 in control register 6. The single ended input is supported in two modes.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Functional Description (continued) C INP1 or INP2 Analog Input C INM1 or INM2 Figure 23. Single-Ended Input Analog Output The OUTP and OUTM are differential output from the DAC channel. The OUTP1 and OUTM1 can drive a load of 600-Ω directly and be either differential or single-ended (see Figure 24).
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Functional Description (continued) Analog Output Configuration (continued) SPEAKER DRIVER CONFIGURATION NO.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between ACD starting (reset) and the FSD going high. During the next 64 MCLKs, the device counts the number of clocks till FS is pulled low. The sum total of the counts in the first phase and the second phase is the number of devices in the channel.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Table 1.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Write Mode Default/Broadcast (00000/11111) 7 Bit S/Sr I2C Device Address (3 Bit)+ 1 Bit 8 Bit R/W Ack Dtdmsp Device Address (+) Increment Index Reg. Address =0 8 Bit Mode (5 Bit) + Index Reg Address (3 Bit) 8 Bit Ack Control Reg. Data (Write) Ack To the Address Given by Index Reg. Address Control Reg. Data (Write) To the Address Given by Index Reg.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Digital Interface Clock Source (MCLK, SCLK) MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout the device. SCLK is the bit clock used to receive and transmit data synchronously.
PAGE 32
TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 the master's FS. The master FSD is output to the first slave and the first slave's FSD is output to the second slave device and so on. When the codecs are configured in cascade mode, MCLK must be connected in star configuration to ensure that MCLK can propagate simultaneously to all the codecs in the chain in less then 2 ps.
PAGE 33
TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency) The 'AIC1x SMARTDM supports a different sampling frequency between the codecs in cascade connecting to a single serial port. All codecs are required to have a common frame synch frequency. The FS signal is calculated using step 1.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Master FS DIN/DOUT Master Slave2 Slave1 Slave0 Master Slave2 Master FSD, Slave 2 FS Slave 2 FSD, Slave 1 FS Slave 1 FSD, Slave 0 FS Slave 0 FSD, (see Note) A. NOTE: Slave 0 FSD should be pulled high for stand-alone-master or cascade configuration. FSD must be pulled low for stand-alone-slave configuration. Figure 33.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Slot Number 0 1 2 2n-3 2n-2 2n-1 Slave 2 Slave 1 Slave 0 SCLK 16 SCLKs Per Slot FS DIN/ DOUT Master Slave n-2 Slave n-3 Slave Slave 2 1 Slave Master Slave 0 n-2 Data Frame Slave n-3 Control Frame (Register R/W) NOTE: n is the total number of AIC12s in the cascade Figure 35.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Slot Number 0 1 2 n-3 n-2 n-1 0 1 2 n-3 n-2 Slave 2 Slave 1 n-1 SCLK 16 SCLKs Per Time Slot FS DIN/ DOUT Master Slave n-2 Slave n-3 Slave Slave 2 1 Slave 0 Master Slave n-2 Data Frame / Sample 1 Slave n-3 Slave 0 Data Frame / Sample 2 NOTE: n is the total number of AIC12s in the cascade Figure 37.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 TURBO PROGRAMMING MODE Stand-Alone Case: •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• Turbo SCLK One SCLK Sampling Period FS Data Frame Control Frame Data Frame Control Frame DIN / DOUT 15 14 ... 1 0 15 14 ... Hi-Z 1 0 15 14 ... 1 0 15 14 ...
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Data Frame Format DIN (15+1) Bit Mode (Continuous Data Transfer Mode Only) D0 D15 - D1 Control Frame Request A/D and D/A Data DOUT (16 Bit A/D Data) D15 - D0 DIN 16 Bit Mode D15 - D0 A/D and D/A Data DOUT 16 Bit Mode D15 - D0 Figure 39.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Master FS Data Frame Slave0 DIN Time Slot A.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Control Register Content Description Control Register 1 (1) (1) D7 D6 D5 D4 D3 D2 D1 D0 ADOVF CX IIR DAOVF BIASV ALB DLB DAC16 R R/W R/W R R/W R/W R/W R/W NOTE: R = Read, W = Write Control Register 1 Bit Summary RESET FUNCTION VALUE BIT NAME D7 ADOVF 0 ADC over flow. This bit indicates whether the ADC is overflow. ADOVF = 0 No overflow.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Control Register 2 Bit Summary (continued) RESET FUNCTION VALUE BIT NAME D2 GPO 0 General-purpose output D1-D0 HPC 00 Host port control bits. Write the following values into D1-D0 to select the appropriate configuration for two pins SDA and SCL. The SDA pin is set to be equal to D2 if D1-D0 = 10.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Table 5.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Table 5.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Table 6.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Control Register 6 D7 D6 D5 PSDO MUTE2 MUTE3 R/W R/W R/W D4 D3 D2 R/W R/W ODRCT R/W D1 AINSEL D0 Reserved R/W R/W Control Register 6 Bit Summary RESET FUNCTION VALUE BIT NAME D7 PSDO 0 Programmable single-ended/differential output. This bit configures the two pins of OUTP2 and OUTP3 as single-ended or differential output.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 IOVDD IOVDD BIAS 1 kΩ 1 kΩ TLV320AIC12 Microphone M/S TLV320C5X FSD MICIN 0.1 µF FSK FS FSR INP1 0.1 µF DIN DX DOUT DR INM1 0.1 µF CLKR INP2 SCLK 0.1 µF CLKX INM2 0.1 µF OUTP1 600 Ω OUTM1 3.3 V Analog Supply 0.1 µF Analog GND RESET From DSP PWRDN From DSP OUTP2 SDA OUTMV SCL OUTP3 DVDD AVDD IOVDD 1 kΩ I2C Master S2C To 1.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 IOVDD IOVDD TLV320AIC12 Microphone BIAS 1 kΩ 1 kΩ M/S TLV320C5X FSD MICIN 0.1 µF FSK FS FSR INP1 0.1 µF DIN DX DOUT DR INM1 0.1 µF CLKR INP2 SCLK 0.1 µF CLKX INM2 MCLK 0.1 µF OUTP1 600 Ω 600 Ω 1 µF 1 µF OUTM1 OUTP2 OUTMV 3.3 V Analog Supply 0.
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TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K www.ti.com SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Layout and Grounding Guidelines for TLV320AIC1x TLV320AIC1x has an in-built analog antialias filter, which provides rejection to external noise at high frequencies that may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC12CDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TLV320AIC12IDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TLV320AIC12KIDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC12CDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 TLV320AIC12IDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 TLV320AIC12KIDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 TLV320AIC12KIRHBT VQFN RHB 32 250 210.0 185.0 35.0 TLV320AIC13CDBTR TSSOP DBT 30 2000 367.0 367.0 38.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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