Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTLV320AIC22CPT

www.ti.com

FEATURES

APPLICATIONS

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Low-Power, Highly-Integrated, Programmable

16-Bit, 26-KSPS, Dual-Channel CODEC

• Differential and Single-Ended Analog

Input/Output

• Stereo 16-Bit Oversampling Sigma-Delta A/D

Converter • Built-In Analog Functions:

• Stereo 16-Bit Oversampling Sigma-Delta D/A – Analog and Digital Sidetone

Converter

– Antialiasing Filter (AAF)

• Support Maximum Master Clock of 100 MHz to

– Programmable Input and Output Gain

Allow DSPs Output Clock to be Used as a

Control (PGA)

Master Clock

– Microphone/Handset/Headset Amplifiers

• Selectable FIR/IIR Filter With Bypassing

– AIC20/21/20K Have a Built-In 8- Ω Speaker

Option

Driver

• Programmable Sampling Rate up to:

– Power Management With Hardware/Software

– Max 26 Ksps With On-Chip IIR/FIR Filter

Power-Down Modes 30 µW

– Max 104 Ksps With IIR/FIR Bypassed

• Separate Software Control for ADC and DAC

• On-Chip FIR Produced 84-dB SNR for ADC Power Down

and 92-dB SNR for DAC over 13-Khz BW

• Fully Compatible With Common TMS320

DSP

• Smart Time Division Multiplexed ( SMARTDM

) Family and Microcontroller Power Supplies

Serial Port

– 1.65-V - 1.95-V Digital Core Power

– Glueless 4-Wire Interface to DSP

– 1.1-V - 3.6-V Digital I/O

– Automatic Cascade Detection (ACD)

– 2.7-V - 3.6-V Analog

Self-Generates Master/Slave Device

• Internal Reference Voltage (V

ref

)

Addresses

• 2s Complement Data Format

– Programming Mode to Allow On-The-Fly

• Test Mode Which Includes Digital Loopback

Reconfiguration

and Analog Loopback

– Continuous Data Transfer Mode to Minimize

Bit Clock Speed

– Support Different Sampling Rate for Each

• Wireless Accessories

Device

• Hands-Free Car Kits

– Turbo Mode to Maximize Bit Clock For

• VOIP

Faster Data Transfer and Allow Multiple

• Cable Modem

Serial Devices to Share the Same Bus

• Speech Processing

– Allows up to Eight Devices to be Connected

to a Single Serial Port

• Host port

– 2-Wire Interface

– Selectable I

C or S

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SMARTDM, TMS320, TMS320C5000, TMS320C6000 are registered trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (56 pages)

PAGE 1
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.
PAGE 2
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-performance, dual-voice codec.
PAGE 3
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.
PAGE 4
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Terminal Functions (continued) TERMINAL NO. I/O M/S NAME 21 I Master slave select applied to CODEC1 only. CODEC2 is always a slave. MCLK 22 I Master clock RESET 23 I Reset VSS 24 I Device ground. Typically this should be connected to the Analog Ground.
PAGE 5
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Electrical Characteristics All specifications are common across the AIC20, AIC21, AIC24, AIC25, AIC20K, and AIC24K except where explicitly stated. AIC20/21/24/25: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V (Unless Otherwise Noted) AIC20K/24K: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.
PAGE 6
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Digital Inputs and Outputs FS = 8 KHz, outputs not loaded PARAMETER MIN TYP MAX UNIT VOH High-level output voltage, DOUT 0.8 IOVDD VOL Low-level output voltage, DOUT V IIH High-level input current, any digital input 5 µA IIL Low-level input current, any digital input 5 µA Ci Input capacitance 3 pF Co Output capacitance 5 pF 0.
PAGE 7
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.
PAGE 8
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 DAC DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS AIC20/21/24/25 MIN TYP AIC20k/24k MAX MIN TYP MAX UNIT The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. DAC Line Output (LINEO-, LINEO+) The test is measured at output of the application schematic low-pass filter.
PAGE 9
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 DAC CHANNEL CHARACTERISTICS PARAMETER TEST CONDITIONS Dynamic range MIN VI = 0 dB at 1020 Hz Interchannel isolation EG Gain error, 0 dB VO = 0 dB at 1020 Hz Mute attenuation PGA = Mute Common-mode voltage Output offset voltage at OUTP1_150 (differential) VO Analog output voltage, (3.
PAGE 10
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 POWER-CONSUMPTION PARAMETER AIC20/21/24/25/20k/24k TEST CONDITIONS MIN TYP ADC (single channel) DAC (single channel) Speaker driver MAX UNIT 5.7 (1) Without drivers 3.5 No signal 9.3 Handset driver No signal 2 Headset driver No signal 2 Lineout driver No signal 2 Reference mW 2.3 Digital PLL Total Analog with all sections on PLL off 3.4 Analog 4.
PAGE 11
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Block Diagram - AIC20/21/20K Speaker 8 Ω Output Line Output 600 Ω Handset 150 Ω Output Handset Input SPKO+ SPKO- LINE0+ LINEO- CODEC 1 (Channel 1) HNSO+ Σ-∆ DAC + HNSO- Analog Sidetone -9 dB to -27 dB 0dB to -42 dB (1.5 dB Steps).
PAGE 12
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Block Diagram - AIC24/25/24K Line Output 600 Ω 150 Ω Output OUTP1 OUTM1 CODEC 1 (Channel 1) OUTP2 Σ−∆ DAC + OUTM2 Input Analog Sidetone −9 dB to −27 dB 0 dB to −42 dB (1.5 dB Steps). −48 dB, −54 dB INP2 INM2 Σ−∆ ADC 150 Ω Output OUTP3 + 0 dB to 42 dB (1.5 dB Steps).
PAGE 13
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Block Diagram (One of Two Channels Shown) CODEC Decimation Filter AntiAliasing Filter PGA SigmaDelta ADC Sinc Filter FIR Filter SMARTDM Serial Port IIR Filter 0 dB to 42 dB (1.
PAGE 14
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 TIMING REQUIREMENTS twH 2.4 V MCLK 2.4 V twL tsu1 th1 2.4 V RESET Figure 1. Hardware Reset Timing SCLK td1 td2 td2 td1 FS FSD td3 ten DOUT tdis D15 tsu2 th2 DIN D15 Figure 2.
PAGE 15
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 SDA tSU;DAT tf tLOW tr tf tHD;STA tBUF tr SCL tHD;STA tHIGH tSU;STA tHD;DAT tSU;STO Figure 3. I2C / S2C Timing Diagram PARAMETER SCL clock frequency Hold time (repeated START condition. After this period, the first clock pulse is generated.
PAGE 16
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 0 500 1000 1500 2000 2500 3000 3500 4000 3500 4000 f − Frequency − Hz Figure 4. FFT—ADC Channel (-3 dB input) 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 0 500 1000 1500 2000 2500 3000 f − Frequency − Hz Figure 5.
PAGE 17
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (continued) 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 f − Frequency − Hz Figure 7. FFT—DAC Channel (-9 dB input) 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 0 2000 4000 6000 8000 10000 f − Frequency − Hz 12000 14000 16000 Figure 8.
PAGE 18
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (continued) 5 Filter Gain − dB 0 −5 −10 −15 −20 −25 −30 0 500 1000 1500 2000 2500 f − Frequency − Hz 3000 3500 4000 3500 4000 Figure 10. ADC FIR Frequency Response - HPF Off Filter Gain − dB 10 0 −10 −20 −30 −40 −50 −60 −70 −80 0 500 1000 1500 2000 2500 f − Frequency − Hz 3000 Figure 11.
PAGE 19
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (continued) Filter Gain − dB 10 0 −10 −20 −30 −40 −50 −60 −70 −80 0 500 1000 1500 2000 2500 3000 3500 4000 14000 16000 f − Frequency − Hz Figure 13. ADC IIR Frequency Response - HPF On 2 Filter Gain − dB 0 −2 −4 −6 −8 −10 −12 −14 0 2000 4000 6000 8000 10000 12000 f − Frequency − Hz Figure 14.
PAGE 20
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (continued) 20 Filter Gain − dB 0 −20 −40 −60 −80 −100 −120 −140 −160 0 1000 2000 3000 4000 5000 6000 7000 8000 28000 32000 f − Frequency − Hz Filter Gain − dB Figure 16. DAC IIR Frequency Response 20 0 −20 −40 −60 −80 −100 −120 −140 −160 −180 −200 0 4000 8000 12000 16000 20000 f − Frequency − Hz 24000 Figure 17.
PAGE 21
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Description Operating Frequencies The sampling frequency is the frequency of the frame sync (FS) signal where falling edge starts digital-data transfer for both ADC and DAC.
PAGE 22
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 www.ti.com Functional Description (continued) 7. Both equations of FS require that the following conditions should be met – (M x N x P) ≤ (devnum mode) if the FIR/IIR filter is not bypassed. – [Integer(M/4) x N x P] ≥ (devnum mode) if the FIR/IIR filter is bypassed.
PAGE 23
www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Description (continued) Analog/Digital Loopback The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output into the analog input where it is then converted by the ADC to a digital word.
PAGE 24
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 www.ti.com Functional Description (continued) IIR/FIR Control Overflow Flags The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog signal has exceeded the range of internal decimation filter calculations.
PAGE 25
www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Description (continued) The Master device always has its FS configured as an output and the last slave in the cascade (i.e. channel with address 0) always has its FSD configured as an input. To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between ACD starting (reset) and the FSD going high.
PAGE 26
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Functional Description (continued) of time slots per frame sync (FS) to match the number of codecs in the serial interface so that no time slot is wasted. Both the programming mode and the continuous data transfer mode of the TLV320AIC2x are compatible with the TLV320AIC12.
PAGE 27
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 0 1 29 30 31 SCLK (Output) 32 SCLKs FS DIN/DOUT (16 Bit) D15 D14 D1 MSB D0 LSB Master (CH 1) D15 D14 D1 MSB D0 LSB Slave (CH 2) Figure 19. Timing Diagram for FS in the Continuous Transfer Mode Cascade Mode and Frame-Sync Delayed (FSD) In cascade mode, the DSP should be in slave mode, i.e.
PAGE 28
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 To CLKOUT or External Oscillator CLKOUT DR DX FSX FSR MCLK FS TLV320AIC20 DIN 1 DOUT SCLK CLKX CLKR FSD TMS320C5X TMS320C6X M/S 3.3 V FS MCLK TLV320AIC20 DIN 2 DOUT SCLK FSD FS M/S MCLK TLV320AIC20 DIN 3 DOUT SCLK FSD FS M/S MCLK TLV320AIC20 DIN 4 DOUT SCLK FSD M/S IOVDD Figure 20.
PAGE 29
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 For validating the conversion data from this operation: • For DAC: The DSP needs to give the same data for n1 samples. CH1 picks one of the n1 samples. • For ADC: CH1 gives the same data for the n1 samples. DSP should pick one of the n1 samples.
PAGE 30
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 SCLK 64 SCLKS FS Control Frame Data Frame Slot 0 CH1 16-Bit DAC DIN CH1 16-Bit ADC DOUT Slot 1 CH2 16-Bit DAC Slot 2 CH1 Register Data Slot 3 CH2 Register Data CH2 16-Bit ADC CH1 Register Data CH2 Register Data Figure 23.
PAGE 31
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com Slot Number SLAS363D – MARCH 2002 – REVISED APRIL 2005 0 1 2 n-3 n-2 n-1 0 1 2 n-3 n-2 Slave 3 Slave 2 n-1 SCLK 16 SCLKs Per Time Slot FS DIN/ DOUT Master Slave n-1 Slave n-2 Slave 3 Data Frame / Sample 1 Slave 2 Slave Master Slave 1 n-1 Slave n-2 Slave 1 Data Frame / Sample 2 NOTE: n/2 is the total number of AIC20s in the cascade Figure 26.
PAGE 32
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.
PAGE 33
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register Programming Each channel in the TLV320AIC2x contains six control registers that are used to program available modes of operation. All register programming occurs during the control frame through DIN. New configuration takes effect after a delay of one frame sync. The TLV320AIC2x is defaulted to the programming mode upon power up.
PAGE 34
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Data to be Written Into Register DIN (Write) D15 D14 D13 0 D11 1 1 D7 - D0 1 Register R/W Broadcast Address DIN (Read) D15 D14 D13 1 SMARTDM Device Address DOUT (Read) 1 X Don’t care 1 1 Register Address D15 D14 D13 D12 D11 D10 D9 D7 - D0 Register Content 0 D7 - D0 Figure 29.
PAGE 35
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Table 2.
PAGE 36
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 I2C • Each I2C read-from or write-to each codec control register is given by an index register address. • Read/write sequence always starts with the first byte as I2C address followed by 0. During the second byte, default/broadcast mode is set and the index register address is initialized.
PAGE 37
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com • SLAS363D – MARCH 2002 – REVISED APRIL 2005 S/Sr -> Start/Repeated Start.
PAGE 38
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register Content Description Control Register 1 (1) (1) D7 D6 D5 D4 D3 D2 D1 D0 ADOVF CX IIR DAOVF BIASV ALB DLB DAC16 R R/W/S R/W R R/W/S R/W R/W R/W/S NOTE: R = Read, W = Write, S = Shadowed Control Register 1 Bit Summary BIT NAME RESET VALUE D7 ADOVF 0 ADC over flow. This bit indicates whether the ADC is overflow.
PAGE 39
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register 2 Bit Summary (continued) BIT NAME RESET VALUE D2 GPO 0 General-purpose output 00 Host port control bits. Write the following values into D1-D0 to select the appropriate configuration for two pins SDA and SCL. The SDA and SCL pins are used for I2C interface if D1-D0 = 00. The SDA and SCL pins are used for S2C interface if D1-D0 = 01.
PAGE 40
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register 3C (1) D7 D6 D5 10 D4 Reserved R/W (1) D3 D2 D1 D0 ICID OSR R/W/S R/W NOTE: R = Read, W = Write, S = Shadowed Control Register 3C Bit Summary BIT NAME RESET VALUE D5 Reserved 0 FUNCTION D4-D2 ICID 000 Chip ID. These two bits represent the device version number.
PAGE 41
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register 4 Bit Summary (continued) BIT NAME D6-D0 MNP RESET VALUE FUNCTION Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequency according to the formula: FS = MCLK / (16 x M x N x P) where: M = 1, 2, ..
PAGE 42
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Table 5. A/D PGA Gain (continued) D5 D4 D3 D2 D1 D0 ADPGA 0 0 0 1 0 0 ADC input PGA gain = 6 dB 0 0 0 0 1 1 ADC input PGA gain = 4.5 dB 0 0 0 0 1 0 ADC input PGA gain = 3 dB 0 0 0 0 0 1 ADC input PGA gain = 1.
PAGE 43
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.
PAGE 44
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Control Register 6A Bit Summary BIT NAME RESET VALUE D6 HDSI2O 0 Headset input to output HDSI2O = 0 The headset input is not connected to the headset output. HDSI2O = 1 The headset input is connected to the headset output. D5 HNSI2O 0 Handset input to output HNSI2O = 0 The handset input is not connected to the handset output.
PAGE 45
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Layout and Grounding Guidelines for TLV320AIC2x TLV320AIC2x has a built-in analog antialias filter, which provides rejection to external noise at high frequencies that may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise.
PAGE 46
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Layout and Grounding Guidelines for TLV320AIC2x (continued) 68 kW LINEI+ 10 kW 68 kW LINEI- 10 kW 136 kW Line 136 kW 300 W LINEO+ 300 W LINEO- 600 W Figure 35. Hybrid Circuit External Connections Microphone, Handset, and Headset External Connections The microphone, headset, and handset external connections are shown in Figure 36.
PAGE 47
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Layout and Grounding Guidelines for TLV320AIC2x (continued) CallerID Interface The callerID amplifier interface to the telephone line is shown in (A). The value for Rx is 365 kΩ (E96 series, which has 1% tolerance). Cx is 470 pF (10% tolerance) of high-voltage rating. Voltage rating is decided based on the telecommunication standards of the country. The typical value is 1 kV.
PAGE 48
TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K www.ti.com SLAS363D – MARCH 2002 – REVISED APRIL 2005 Layout and Grounding Guidelines for TLV320AIC2x (continued) IOVDD TLV320AIC20 12 1 µF 0.1 µF IOVDD 0.01 µF 13 IOVSS DGND DVDD 15 0.1 µF AVDD2 0.1 µF 0.01 µF 16 DVSS DGND 5 0.1 µF DRVDD DVDD 6 AVDD2 AVSS2 AGND 27 0.1 µF 25 AGND 29 DRVDD DRVSS1 DRVSS2 AVDD 33 0.1 µF AVDD 32 AVDD1 AVSS1 AGND 42 0.
PAGE 49
PACKAGE OPTION ADDENDUM www.ti.
PAGE 50
PACKAGE OPTION ADDENDUM www.ti.
PAGE 51
PACKAGE OPTION ADDENDUM www.ti.
PAGE 52
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC20CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TLV320AIC20IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TLV320AIC20KIPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
PAGE 53
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC20CPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TLV320AIC20IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TLV320AIC20KIPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TLV320AIC21CPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TLV320AIC21IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 TLV320AIC24CPFBR TQFP PFB 48 1000 367.
PAGE 54
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 55
PAGE 56
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.