! " # # $ ! %$& ' Data Manual February 2004 Digital Audio Products SLWS106H
Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . .
.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11 A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure 2−1 2−2 2−3 2−4 2−5 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 3−18 3−19 3−20 3−21 3−22 3−23 3−24 3−25 3−26 Title System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-Wire Control Interface Timing Requirements .
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1 Introduction The TLV320AIC23B is a high-performance stereo audio codec with highly integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported.
− − − • Integrated Total Electret-Microphone Biasing and Buffering Solution − − − • Low-Noise MICBIAS pin at 3/4 AVDD for Biasing of Electret Capsules Integrated Buffer Amplifier With Tunable Fixed Gain of 1 to 5 Additional Control-Register Selectable Buffer Gain of 0 dB or 20 dB Stereo-Line Inputs − − Integrated Programmable Gain Amplifier Analog Bypass Path of Codec • ADC Multiplexed Input for Stereo-Line Inputs and Microphone • Stereo-Line Outputs − Analog Stereo Mixer for DAC and Analog Bypass
1.2 Functional Block Diagram VMID VMID AVDD 1.0X 50 kΩ DSPcodec TLV320AIC23B VDAC 1.0X VADC 50 kΩ 1.0X AGND CS Control Interface 1.5X MICBIAS SDIN SCLK MODE 12 to −34.5 dB, 1.5 dB Steps Σ−∆ ADC 2:1 MUX Line Mute RLINEIN Bypass Mute, Mute 0 dB, 20 dB 50 kΩ 10 kΩ VADC MICIN VMID 12 to −34 dB, 1.
1.
1.4 Ordering Information PACKAGE TA 32-Pin MicroStar Junior GQE/ZQE 28-Pin TSSOP PW 28-Pin PQFP RHD −10°C to 70°C TLV320AIC23BGQE/ZQE TLV320AIC23BPW TLV320AIC23BRHD −40°C to 85°C TLV320AIC23BIGQE/ZQE TLV320AIC23BIPW TLV320AIC23BIRHD 1.5 Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION GQE/ ZQE PW RHD AGND 5 15 12 Analog supply return AVDD 4 14 11 BCLK 23 3 28 Analog supply input. Voltage level is 3.3 V nominal. I2S serial-bit clock.
1.5 Terminal Functions (continued) TERMINAL NO. I/O DESCRIPTION 21 I Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See Section 3.1 for details. 23 20 I Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is used to select the control protocol after reset. See Section 3.1 for details. 6 16 13 I Midrail voltage decoupling input. 10-µF and 0.
2 Specifications 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3 .
2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/MCLK = 256fs, fs = 48 kHz (unless otherwise stated) 2.3.1 ADC 2.3.1.1 Line Input to ADC PARAMETER TEST CONDITIONS MIN Input signal level (0 dB) TYP MAX 1 fs = 48 kHz (3.3 V) fs = 48 kHz (2.7 V) Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4) 85 90 dB 90 Dynamic range, A-weighted, −60-dB full-scale input (see Note 4) AVDD = 3.3 V AVDD = 2.
2.3.1.3 Microphone Bias PARAMETER TEST CONDITIONS Bias voltage MIN TYP MAX 3/4 AVDD − 100 m 3/4 AVDD 3/4 AVDD + 100 m V 3 mA Bias-current source Output noise voltage 2.3.2 1 kHz to 20 kHz UNIT 25 nV/√Hz DAC 2.3.2.1 Line Output, Load = 10 kΩ, 50 pF PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage (FFFFFF) MAX 1.0 Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5) AVDD = 3.3 V AVDD = 2.7 V Dynamic range, A-weighted (see Note 4) AVDD = 3.3 V AVDD = 2.
2.3.4 Stereo Headphone Output PARAMETER TEST CONDITIONS MIN 0-dB full-scale output voltage TYP MAX 1.0 Maximum output power, PO RL = 32 Ω 30 RL = 16 Ω 40 Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 Total harmonic distortion AVDD = 3.3 V, 1 kHz output Power supply rejection ratio 1 kHz, 100 mVpp Programmable gain 1 kHz output mW 97 dB PO = 10 mW PO = 20 mW 0.1 1.
2.4 Digital-Interface Timing PARAMETER MIN High 18 Low 18 tw(1) tw(2) System-clock pulse duration, MCLK/XTI tc(1) System-clock period, MCLK/XTI MAX Propagation delay, CLKOUT UNIT ns 54 Duty cycle, MCLK/XTI tpd(1) TYP ns 40/60% 60/40% 0 10 ns tc(1) tw(1) tw(2) MCLK/XTI tpd(1) CLKOUT CLKOUT (Div 2) Figure 2−1. System-Clock Timing Requirements 2.4.
2.4.2 Audio Interface (Slave-Mode) PARAMETER tw(3) tw(4) Pulse duration, BCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(2) tpd(4) Clock period, BCLK 50 tsu(2) th(2) Setup time, DIN 10 ns Hold time, DIN 10 ns tsu(3) th(3) Setup time, LRCIN 10 ns Hold time, LRCIN 10 ns Propagation delay, DOUT 0 tc(2) tw(4) tw(3) BCLK LRCIN LRCOUT tsu(2) th(3) tsu(3) DIN tpd(2) th(2) DOUT Figure 2−3.
2.4.3 Three-Wire Control Interface (SDIN) PARAMETER tw(5) tw(6) Clock pulse duration, SCLK MIN High 20 Low 20 TYP MAX UNIT ns tc(3) tsu(4) Clock period, SCLK 80 ns Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) th(4) Setup time, SDIN to SCLK 20 ns 20 ns tw(7) tw(8) Hold time, SCLK to SDIN Pulse duration, CS High 20 Low 20 ns tw(8) CS tc(3) tw(5) tw(6) tsu(4) SCLK tsu(5) th(4) LSB DIN Figure 2−4. Three-Wire Control Interface Timing Requirements 2.4.
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3 How to Use the TLV320AIC23B 3.1 Control Interfaces The TLV320AIC23B has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level. 3.1.
The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2). The 16-bit control word is divided into two parts.
Right Line Input Channel Volume Control (Address: 0000001) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0 Default 0 1 0 0 1 0 1 1 1 RLS Right/left line simultaneous volume/mute update Simultaneous update 0 = Disabled 1 = Enabled Right line input mute 0 = Normal 1 = Muted Right line input volume control (10111 = 0 dB default) 11111 = +12 dB down to 00000 = –34.5 dB in 1.
INSEL MICM MICB Input select for ADC Microphone mute Microphone boost X Reserved 0 = Line 0 = Normal 0=dB 1 = Microphone 1 = Muted 1 = 20dB Digital Audio Path Control (Address: 0000101) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X DACM DEEMP1 DEEMP0 ADCHP Default 0 0 0 0 0 1 0 0 0 DACM DEEMP[1:0] ADCHP X DAC soft mute De-emphasis control ADC high-pass filter Reserved 0 = Disabled 00 = Disabled 1 = Disabled 1 = Enabled 01 = 32 kHz 0 = Enabled 10 = 44.
Sample Rate Control (Address: 0001000) BIT D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 1 0 0 0 0 0 CLKIN CLKOUT SR[3:0] BOSR Clock input divider 0 = MCLK 1 = MCLK/2 Clock output divider 0 = MCLK 1 = MCLK/2 Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.
3.2.2 Microphone Input MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It has a programmable volume control and a mute function. Active and passive filters prevent high frequencies from folding back into the audio band. The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 = 50 k/(10 k + RMIC).
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated. The gain is independently programmable on the left and right channels. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3). 3.2.
1/fs LRCIN/ LRCOUT BCLK Left Channel DIN/ n n−1 1 Right Channel 0 n n−1 1 0 n DOUT MSB LSB Figure 3−6. Left-Justified Mode Timing 3.3.1.3 I2S Mode In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT (see Figure 3-7). 1/fs LRCIN/ LRCOUT BCLK 1BCLK DIN/ DOUT Left Channel n n−1 1 MSB Right Channel 0 n n−1 1 0 LSB Figure 3−7. I2S Mode Timing 3.3.1.4 DSP Mode The DSP mode is compatible with the McBSP ports of TI DSPs.
3.3.2 Audio Sampling Rates The TLV320AIC23B can operate in master or slave clock mode. In the master mode, the TLV320AIC23B clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB specification. The TLV320AIC23B can be used directly in a USB system. In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control the TLV320AIC23B clock and sampling rates.
3.3.2.2 Normal-Mode Sampling Rates In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available: MCLK = 12.288 MHz SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS ADC (kHz) DAC (kHz) FILTER TYPE SR3 SR2 SR1 SR0 BOSR 96 96 2 0 1 1 1 0 48 48 1 0 0 0 0 0 32 32 1 0 1 1 0 0 8 8 1 0 0 1 1 0 48 8 1 0 0 0 1 0 8 48 1 0 0 1 0 0 MCLK = 11.
3.3.3 Digital Filter Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Characteristics ( TI DSP 250 fs Mode Operation ) Passband ±0.05 dB Stopband −6 dB 0.416 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple f > 0.584 fs −60 dB dB ADC Filter Characteristics ( TI DSP 272 fs and Normal Mode Operation ) Passband ±0.05 dB Stopband −6 dB 0.4535 fs Hz 0.5 fs Stopband attenuation Hz ±0.05 Passband ripple dB f > 0.5465 fs −60 dB −3 dB, fs = 44.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.1 0.2 0.3 0.4 0.5 Normalized Audio Sampling Frequency Figure 3−9. Digital De-Emphasis Filter Response − 44.1 kHz Sampling FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY 0 Filter Response − dB −2 −4 −6 −8 −10 0 0.10 0.20 0.30 0.40 0.50 Normalized Audio Sampling Frequency Figure 3−10.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 2 1.5 2.5 3 Normalized Audio Sampling Frequency Figure 3−11. ADC Digital Filter Response 0: USB Mode (Group Delay = 12 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−12.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2.5 2 3 Normalized Audio Sampling Frequency Figure 3−13. ADC Digital Filter Response 1: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Normalized Audio Sampling Frequency Figure 3−14. ADC Digital Filter Ripple 1: USB Mode Only 3−14 0.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−15. ADC Digital Filter Response 2: USB mode and Normal Modes (Group Delay = 3 Output Samples) FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−16.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−17. ADC Digital Filter Response 3: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Normalized Audio Sampling Frequency Figure 3−18. ADC Digital Filter Ripple 3: USB Mode Only 3−16 0.45 0.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 Normalized Audio Sampling Frequency 2.5 3 Figure 3−19. DAC Digital Filter Response 0: USB Mode FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−20.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−21. DAC Digital Filter Response 1: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Normalized Audio Sampling Frequency Figure 3−22. DAC Digital Filter Ripple 1: USB Mode Only 3−18 0.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−23. DAC Digital Filter Response 2: USB Mode and Normal Modes FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−24.
FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 10 −10 −30 −50 −70 −90 0 0.5 1 1.5 2 2.5 3 Normalized Audio Sampling Frequency Figure 3−25. DAC Digital Filter Response 3: USB Mode Only FILTER RESPONSE vs NORMALIZED AUDIO SAMPLING FREQUENCY Filter Response − dB 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Audio Sampling Frequency Figure 3−26.
Appendix A Mechanical Data GQE/ZQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. ∅ 0,05 M 0,21 0,11 0,08 4200461/C 10/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments.
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°−ā 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. A−2 All linear dimensions are in millimeters. This drawing is subject to change without notice.
RHD (S−PQFP−N28) PLASTIC QUAD FLATPACK 5,00 A B ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ 5,00 28 1 PIN 1 INDEX AREA 1,00 0,80 0,20 REF C SEATING PLANE 0,08 C 3,25 SQ 3,00 PIN 1 IDENTIFIER 0,05 MAX 1 0,65 28 0,45 0,435 28 0,18 0,435 4 3,00 0,18 0,50 EXPOSED THERMAL DIE PAD D 28 0,30 0,18 0,10 M C A B 4204400/A 05/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. QFN (Quad Flatpack No−Lead) Package configuration.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC23BIPWR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 TSSOP PW 28 2000 330.0 16.4 6.9 TLV320AIC23BIRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC23BPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC23BIPWR TSSOP PW 28 2000 367.0 367.0 38.0 TLV320AIC23BIRHDR VQFN RHD 28 3000 338.1 338.1 20.6 TLV320AIC23BPWR TSSOP PW 28 2000 367.0 367.0 38.0 TLV320AIC23BRHDR VQFN RHD 28 3000 338.1 338.1 20.6 TLV320AIC23BZQER BGA MICROSTAR JUNIOR ZQE 80 2500 338.1 338.1 20.
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